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Analysis

  • CDR for USB 3.0 PHY

    Sir, I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic...
    Posted to Custom IC Design (Forum) by Jithin on Tue, May 20 2014
  • Phase noise plot

    Hi, I have been doing a Pnoise analysis . Unfortunately I was unable to plot the phase noise response. My design was setup was described below. My apparatus was a PLL with a fixed divider ratio of 20 and output frequency of 500Mz In PSS analysis I have set the beat frequency as reference frequency ie...
    Posted to Custom IC Design (Forum) by Jithin on Wed, Apr 10 2013
  • Re: Problem in Cadence Virtuoso AC analysis

    Hi Andrew, I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing. As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating...
    Posted to Custom IC Design (Forum) by OneNewBoy on Mon, Mar 25 2013
  • Pnoise analysis

    Hi, I have been designing a PLL which gives an output frequency in the range (400-500)MHz to the reference input frequency of (20-25)MHz.So for doing the pnoise analysis I have added the PSS as well as Pnoise analysis I have made the following as setup for the analysis for a frequency of 500MHz. I have...
    Posted to Custom IC Design (Forum) by Jithin on Sun, Mar 3 2013
  • Simulating Crystal Oscillators is Much Easier in MMSIM12.1 - Part 2

    Greetings, Simulating crystal oscillators got a lot easier in MMSIM12.1... We have made enhancements to both Harmonic Balance and transient analyses. In Part 1 , I discussed Improvements to the Harmonic Balance use model. With the new streamlined Choosing Analyses form, you now can focus on getting your...
    Posted to RF Design (Weblog) by Tawna on Thu, Dec 20 2012
  • Pspice problem - Remove DC offset from analysis

    Hello! I'm using OrCAD 16.5 lite student version for doing some BJT analysis for university. How do I remove the DC portion of the signal I view on PSPICE? It is the collector voltage of a very simple common emitter amplifier. I want to compare the output with the input in order to graph them and...
    Posted to PCB Design (Forum) by pppppp on Tue, Aug 28 2012
  • DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

    In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 14 2012
  • Aborting transient analysis after desired value is found

    I am simulating a floating gate memory model custom made in verilog. I am running several simulations using an Ocean script with varying parameters to determine total charge, time to reach total charge, retention time, etc. All of these must be done with transient analysis. My question is how do I abort...
    Posted to Custom IC SKILL (Forum) by JayJetz on Tue, Apr 19 2011
  • New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

    Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 31 2011
  • Measure Twice, Cut Once for Transistor ft

    Recently there was an inquiry about the methodology for performing the f t (transition frequency) versus Ic measurement described in my Measuring Transistor f t blog post from July 2008: By bid75 on September 8, 2010 I am unable to understand how ft vs. Ic plot is generated. How do you do a nested sweep...
    Posted to RF Design (Weblog) by Art3 on Wed, Oct 6 2010
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