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12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Modeling Oscillators with Arbitrary Phase Noise Profiles
When you need to include noisy oscillators in SpectreRF transceiver simulations, you have at least 3 options: 1) Semi-autonomous simulation is the most accurate approach, recommended whenever the transistor-level model of the oscillator is available. 2) rfLib/osc model is less accurate but it’s...
Posted to
RF Design
(Weblog)
by
Tawna
on Thu, May 24 2012
Managing Inherited Connections with CPF in Virtuoso
Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...
Posted to
Mixed-Signal Design
(Weblog)
by
AndreasLenz
on Wed, May 23 2012
Things You Didn't Know About Virtuoso: Rapid Adoption Kits
This post isn't directly about tips and tricks for getting the most out of Virtuoso, but it is about a new source of information and hands-on guidance to help you put those tips and tricks into action. They're called Rapid Adoption Kits, or--to use the obligatory Three Letter Acronym (TLA)--RAKs...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Tue, May 22 2012
Measuring 2-Tone Intermodulation Using Envelope-Following Analysis
From time to time, SpectreRF users simulate very large, extracted-view circuits in 2+ tone QPSS. In many of those cases, memory requirements exceed the available resources. When that happens and small-signal approximations aren’t applicable, the user is typically stuck. The solution below and attached...
Posted to
RF Design
(Weblog)
by
Tawna
on Wed, May 16 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 9 2012
Free Webinars Preview 20nm Challenges, Solutions
If you're designing or planning to design at 20nm - or you're just curious about this emerging and much-discussed process node - three free webinars May 1, 2 and 3 will provide a wealth of valuable information. In these webinars, Cadence experts will team up with industry leaders to present 20nm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 12 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups
On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “ Bringing Continuous Domain into SystemVerilog...
Posted to
Mixed-Signal Design
(Weblog)
by
PrabalB
on Fri, Mar 30 2012
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