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Analog artist

  • How to override parameters in the same block - ADEXL Global Variables

    Hello, I was wondering if you could help with the following issue: The vendor's provided model file has a definition for a parameter (param1) which I would like to override. Both definitions would happen in the same "block" (same level). The way I'm trying to do this, with no success...
    Posted to Custom IC Design (Forum) by WMACH on Thu, Apr 17 2014
  • Video: Cadence Founder Jim Solomon on Company History, and What EDA Needs Today

    Although we're celebrating the 25 th anniversary of Cadence this year (2013), the origins of Cadence go back to the early 1980s, with the beginnings of the two companies that merged to form Cadence in 1988—SDA Systems and ECAD. Jim Solomon, a veteran analog designer who launched SDA Systems...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 24 2013
  • 25 Years of Innovation at Cadence – 25 Key Milestones

    Cadence is celebrating its 25 th anniversary in 2013, and there's a long history of innovation to celebrate. We'll be highlighting some of that history over the next 12 months in blogs, videos, and other media. In this post, I'll point to some of the key contributions that Cadence brought...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 17 2013
  • Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling

    A re we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative ( Si2 ) Conference Oct. 9, 2012, he argued that the consumer electronics marketplace will drive a new era he calls "Custom 2.0." The Si2...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 11 2012
  • lvsIgnore, netlistIgnore

    Hello colleagues, I have a question related to IC5.1.41: In a schematic, it is possible to place the property "lvsIgnore" on a component, to exclude his component from LVS. In other words, this component is taken into acount during netlisting and simulation, but not during LVS. my question...
    Posted to Custom IC Design (Forum) by FrankOpteynde on Mon, Oct 3 2011
  • IC5141 ADE scalar results

    Hi, It's there a way to change the format of the scalar results printed in ADE window ? By default it has only 4 numbers, for example 45.78m . I want to be printed as 45.789244m . What should I put in .cdsinit or .cdsenv to change this number format ?? It is possible to print this results in the...
    Posted to Custom IC Design (Forum) by DanySF on Tue, Jul 5 2011
  • Have device connectivity added as an include?

    Hi, Presently, the device connectivity portion of the input file is added as a "cat" function where every single line of the device connectivity shows up as a line in the input file. Is there any hidden switch to change the behavior so that the device connectivity shows up as a single .include...
    Posted to Custom IC Design (Forum) by SharksFan on Fri, Aug 13 2010
  • Monte Carlo Analysis | HitKit

    Hi, I was trying to perform a statistical analysis, but encountered some problems: 1) According to this tutorial : http://asic.austriamicrosystems.com/hitkit/circuit_sim/montecarlo/monte_spectre.html I am supposed to to open Tools -> Monte Carlo in ADE window. Unfotunatelly there is no 'Monte...
    Posted to Custom IC Design (Forum) by pitter on Sat, May 8 2010
  • Tcl Commands to set method of Integration

    Dear All, I am new to this community. Let me introduce as Debjit from India. I am facing the following problem. I want to change the method of integration and/or the errpreset of a simulation during run time. I am able to change the reltol, vabstol, iabstol value during runtime by tcl commands like "analog...
    Posted to Custom IC Design (Forum) by mobileee on Wed, Apr 7 2010
  • About the spectre pss problem

    Hi, deal all: I use the old version of spectre (ver 5.10.41), when I do a vco pss analysis , I found the spectre can't catch the frequency of the vco. For example , before the pss analysis a run a tran analysis. measure the freq=1.4617G(when the vco have reach the stable state);but in the following...
    Posted to Custom IC Design (Forum) by kivvzhou on Mon, Mar 15 2010
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