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Analog and RF SiP design

What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

Currently, many of the SPB products support extended nets, better known as Xnets. Xnets are created automatically when a signal model is assigned to a component and that signal model defines that a connection is to be made between two pins of the component. This creates an Xnet that connects the nets...

Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Aug 8 2011
Favorite Features Of An IC Package Designer: Assembly Rule Checks

This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the question of "Can this be manufactured?"...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Wed, Jul 28 2010
Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence SiP

Is there anyone who does not carry a mobile communication device anymore? Sending and receiving phone calls seem to be just a minor feature on these devices nowadays. With texting, email, Wi-Fi, GPS, camera, video, image recognition software, and many more features available in our hand held devices...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Fri, May 28 2010
Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats

This is the second in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. Recently on a visit to an avid user of IC Package design tools, we heard the requirement mantra of efficiency and flexibility. Many package designers...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Thu, May 20 2010
3D IC or TSV: The Next Phase in Functional Density and Miniaturization

It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD...

Posted to IC Packaging and SiP (Weblog) by SiPper on Thu, Jan 22 2009
TSV, mainstream or niche?

I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries and some iDM's) talking about pilot projects...

Posted to IC Packaging and SiP (Weblog) by SiPper on Wed, Sep 24 2008
Analog/RF chip designers don't care about the Package?

So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!! Now I kinda understand that this could...

Posted to IC Packaging and SiP (Weblog) by SiPper on Mon, Aug 25 2008
Verifying multi-technology chips-in-a-SiP, fact or fiction?

With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?" If you have ever pondered this challenge, or have...

Posted to IC Packaging and SiP (Weblog) by SiPper on Wed, Aug 20 2008

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Analog and RF SiP design

What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

Favorite Features Of An IC Package Designer: Assembly Rule Checks

Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence SiP

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats

3D IC or TSV: The Next Phase in Functional Density and Miniaturization

TSV, mainstream or niche?

Analog/RF chip designers don't care about the Package?

Verifying multi-technology chips-in-a-SiP, fact or fiction?