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Allegro PCb

  • Constraints for fanout

    Hi, I want to create some rules for Allegro PCB when it creates fanout for my BGA. I have defined two types of VIAs and I want to force Allegro to use one VIA - and thick track width - for Power& GND pads and other VIA - with thinner track width - for signals. Where can I define such rules? Any suggestions...
    Posted to PCB Design (Forum) by Hossein1357 on Thu, Jul 31 2014
  • DRC Error: Package to Room Spacing

    Hi everybody, I am designing my PCB (OrCAD 16.6). When I place parts of a room I see below message: Class: DRC ERROR CLASS Subclass: PACKAGE_BOTTOM Origin xy: (1068.00 178.00) Constraint: Package to Room Spacing Constraint Set: NONE Constraint Type: DESIGN Constraint value: 0 MIL Actual value: 65 MIL...
    Posted to PCB Design (Forum) by Hossein1357 on Sat, Jul 26 2014
  • Re: Radial/polar placement !

    To place component as you desire, I tried "Import > Placement" command I calculated coordinates X and Y, setting: a RADIUS value (I used mils for the distance from origin), an ANGLE (degrees between a symbol and the next one), an initial PHASE (degrees, you may want to place the first symbol...
    Posted to PCB Design (Forum) by Alicia on Tue, Feb 4 2014
  • Orcad PCB / Allegro version conversions? (Argh!)

    I know; I should rob a bank and get my 16.2 Orcad PCB upgraded. But I don't really want to develop criminal skills. So I've spend a few days trying to find some way to convert 16.3 (and later) libs and boards to 16.2. And came up with absolutely nothing but a nasty feeling that Cadence is doing...
    Posted to PCB Design (Forum) by N i z e on Wed, Dec 18 2013
  • Why the same net via and shape can not connect togeter?

    I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together. just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot! http://xiangce.baidu.com/picture/detail/8f2f80782f2eeecf44752e05fa10543a59b5931c
    Posted to PCB Design (Forum) by Sunner on Fri, Nov 22 2013
  • How to Add Specially Created Via Padstacks to Just the Design Database vs. Library?

    For a design, trying to keep some specially created via padstacks out of the general library path and instead just keep with the design database. In the Allegro Constraint Manager, there are two options for assigning vias to the nets but it's not clear how to get these new, specially-created via...
    Posted to PCB Design (Forum) by RMS707 on Mon, Jul 22 2013
  • frf file for xilinx Kintex7

    Hello, I search for frf file for xc7k70t, a Kintex7 Xilinx FPGA. I need it to use in FSP program. Where can I find it? Is copying the file to .../tools/fsp/frf/K7 folder enough or should I do anything else? I use Allegro version16.5. thanks
    Posted to PCB Design (Forum) by SoheilMah on Thu, Jun 27 2013
  • Missing Drill symbols on the board

    Hello, I have a situation. I have prepared the PCB layout with no issues but the point i stuck on is, i dont see the drill symbols on the prepared board.. e.g I have a through hole pin connectors on my board, i can see the pad stacks, thermal relief and all other things which are there in the footprint...
    Posted to PCB Design (Forum) by raul5565 on Tue, May 14 2013
  • Copper Pouring and Gloss (is it a problem?)

    Hello, i am designing a microcontroller 2 sided board in Allegro 16.5, after routing all the components, i want to apply the Copper Poring(Power Ground) on both sides. I can do it easily but the problem is, after copper pouring when I use "Gloss" option , the blank spaces which was there between...
    Posted to PCB Design (Forum) by raul5565 on Wed, May 8 2013
  • allegro sp 16.5 lite - "error(spmhod-29)"

    Hi, i'm new to pcb design tool , i received some .brd and .dra and .psm file from my friend for my practice, he did this on Allegro sp 16.6 but i'm using Allegro sp 16.5 lite version. when i open those file i receive the following error. ERROR(SPMHOD-29): Unable to open design because database...
    Posted to PCB Design (Forum) by ping2murali on Wed, Mar 27 2013
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