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Allegro PCb,allegro

  • how to move routed area without any change

    Tool: Allegro PCB Editor 16.3 I have placed all components on a PCB & partially routed. Now I want to move the routed area by 1"down with all connections,footprints, vias & clines. It is a 6 layer PCB. Components are there on top & bottom. Routed nets are there on all signal layers....
    Posted to PCB Design (Forum) by rinj on Tue, Jan 3 2012
  • Re: NetList export from OrCAD to PADS or ALLEGRO

    [quote user="wolfeman"] First how familiar are you with PADS? With PADS (pending version you are using of PADS) you need to export the PADS2000 format pads2K.dll there is a later version you can download that will also some back annotation? I think but if you are using any version of PADS 9...
    Posted to PCB Design (Forum) by PCB EXPERT on Wed, Nov 2 2011
  • NetList export from OrCAD to PADS or ALLEGRO

    Exploring more options to "communicate" through different CAD software. I'm now using Cadence Design Entry CIS to work on the schematic, and would like to export the netlist and import it into PADS and also ALLEGRO board design. For PADS, when I export the netlist through: Tools -->...
    Posted to PCB Design (Forum) by PCB EXPERT on Tue, Oct 18 2011
  • How do you adjust the font size in Allegro dialogs?

    I'm using Allegro on Linux and I'me having trouble adjusting the font size.
    Posted to PCB Design (Forum) by lpsd on Fri, Aug 26 2011
  • fottprint problem in Allegro Package

    Hi there. I created a new fottprint with the wizzard ... I created 4 pins, but needed only three (trimpot) ... now I need to delete 1 pin ... programm does not let me delete the pin ... Question: How do I get rid of the pin! Thanx in advance. systemman
    Posted to PCB Design (Forum) by systemman on Thu, Jun 9 2011
  • RAVEL----Custom DRC System for SiP and PCB

    "RAVEL(Relational Algebra Verification Expression Language) DRC System for SiP and PCB" have Components followed: • RAVEL DRC language – Description and exchange of design rules • RAVEL DRC engine – Checking of design rules coded in RAVEL language in SiP Layout and PCB...
    Posted to PCB Design (Forum) by AllenYang on Fri, May 27 2011
  • How to create drill location report

    Hi all, Can anybody help me, How to create drill location report from a .brd file (Tool: Allegro PCB design 16.3)? Below is an example from an orcad layout plus file. COMMENTS DRILL TOOL XCOORD YCOORD ------------------------------------------------------- Holes (Padstacks with no pads defined) 2.60...
    Posted to PCB Design (Forum) by rinj on Thu, Feb 17 2011
  • Complex antipad shape

    Hello, I need to create a padstack with a complex antipad shape on the signal ground layer (for signal integrity). The shape is easy to draw in autocad, so I did it there. In the Cadence editor, complex shapes are, well, complex, in my experience. Can I import the DXF file I created from Autocad an use...
    Posted to PCB Design (Forum) by jjones5617 on Mon, Dec 13 2010
  • Same net via to via spacing drc suppressed

    In SPB 16.3 hotfix 20 (maybe implemented in 18) Allegro Constraint manager will no longer report a same net via to via spacing drc if those vias are covered (direct connect) by a shape. Cadence says that once the via is covered with a shape the pad ceases to exist and it simply becomes a hole to hole...
    Posted to PCB Design (Forum) by Idaho Tom on Mon, Dec 6 2010
  • line to shape spacing error

    Hi All I have attached a doc .Please go through that doc for clarifying my doubt. I poured a dynamic copper shape for ground over the ground pin which is already connected by tracks. It shows line to shape DRC. Whether i have to add any property to that particular net alone or i have to do it in different...
    Posted to PCB Design (Forum) by Anonymous on Thu, Dec 2 2010
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