Home > Community > Tags > Allegro PCb/DRC error
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Allegro PCb,DRC error

  • DRC Error: Package to Room Spacing

    Hi everybody, I am designing my PCB (OrCAD 16.6). When I place parts of a room I see below message: Class: DRC ERROR CLASS Subclass: PACKAGE_BOTTOM Origin xy: (1068.00 178.00) Constraint: Package to Room Spacing Constraint Set: NONE Constraint Type: DESIGN Constraint value: 0 MIL Actual value: 65 MIL...
    Posted to PCB Design (Forum) by Hossein1357 on Sat, Jul 26 2014
  • Same net via to via spacing drc suppressed

    In SPB 16.3 hotfix 20 (maybe implemented in 18) Allegro Constraint manager will no longer report a same net via to via spacing drc if those vias are covered (direct connect) by a shape. Cadence says that once the via is covered with a shape the pad ceases to exist and it simply becomes a hole to hole...
    Posted to PCB Design (Forum) by Idaho Tom on Mon, Dec 6 2010
  • line to shape spacing error

    Hi All I have attached a doc .Please go through that doc for clarifying my doubt. I poured a dynamic copper shape for ground over the ground pin which is already connected by tracks. It shows line to shape DRC. Whether i have to add any property to that particular net alone or i have to do it in different...
    Posted to PCB Design (Forum) by Anonymous on Thu, Dec 2 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Cadence 14.0 : DRC error Line to SMD Pin Spacing

    Hello, I route a board on Cadence 14.0 and have an unknown problem. Each time I try to connect 2 pins of a same net, I have 2 DRC errors : Line to SMD Pin Spacing. More over, when I connect these 2 pins, it is not automaticaly directed to the center of the second pin. Is thre anyone who can help me ...
    Posted to PCB Design (Forum) by romaric on Wed, Jul 7 2010
Page 1 of 1 (5 items)