Home > Community > Tags > Allegro PCb/Capture CIS/16.3
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Allegro PCb,Capture CIS,16.3

  • How to Export Allegro Design Entry HDL to Capture?

    Hi Everyone, Please help to reply following the question. Thanks. How to Export Allegro Design Entry HDL to Capture? Victor
    Posted to PCB Design (Forum) by 741218 on Thu, Dec 16 2010
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Component placement error in Allegro 16.2

    Hello folks, Allegro keeps giving me an error message everytime i try to Place Manually a symbol (6032 CAP)...the message says: ""E- (SPMHGE-82): Pin numbers do not match between symbol and component. Run dev_check on device file for more information."" I have saved the *.dra file...
    Posted to PCB Design (Forum) by Fadi on Fri, Apr 9 2010
Page 1 of 1 (3 items)