Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > Allegro PCB Editor/PCB Layout and routing/PCB design/Allegro PCB SI
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Allegro PCB Editor,PCB Layout and routing,PCB design,Allegro PCB SI

  • Want to change D2PAK footprint with TO263-3 on Orcad/Allegro PCB Editor

    I have a PCB *.BRD file. No schematic no netlist. On board 03 D2PAK footprint placed U28, U29, U30. I want to replace a only U29 footprint D2PAK with To263-3. Any body know the procedure to replace the footprint without schematic and netlist.
    Posted to PCB Design (Forum) by AamirZ on Tue, Nov 20 2012
  • What's Good About Retaining Electrical Constraints? Look to SPB16.5 and See!

    Currently, many of the SPB products support extended nets, better known as Xnets. Xnets are created automatically when a signal model is assigned to a component and that signal model defines that a connection is to be made between two pins of the component. This creates an Xnet that connects the nets...
    Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Aug 8 2011
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010
  • Regarding Xnet properties getting lost

    Hi, I am currently using 15.7 Allegro PCB Design XL. I have assigned Models to components to assign XNET properties. Whenever iam importing the latest netlist the Xnet properties are getting lost. Our schematic engineers are using Mentor Dx Designer to generate netlist in .tel format. Every time I import...
    Posted to PCB Design (Forum) by kingshar on Wed, May 26 2010
Page 1 of 1 (4 items)