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Allegro PCB Editor,16.2

  • How to change package design(.dra) to reflect in layout after placement of component is done

    I have made some modifications in the package file of a component (say changed the silkscreen or place bound), So I know by ECO mode the changes I made are getting reflected in the library. But if suppose I have placed the components already, in the board layout(.brd) , those changes are not getting...
    Posted to PCB Design (Forum) by Varun1610 on Sun, Jun 16 2013
  • how to create a schematic from a pcb

    Can I create a schematic from a .brd file? I guess the schematic went missing. Cadence 16.3 PCB and Cadence 16.3 Design entry HDL. thanks! Dana
    Posted to PCB Design (Forum) by Dana on Fri, Aug 24 2012
  • Re: Can't place parts in Orcad PCB... Solved! :-)

    Thanks to NordCad for the solution! You/I should be seeing check boxes to the left of refdes in the manual placement dialogue box! I didn't. It seems this is a issue with Windows 7. The text of the dialogue boxes is a bitmapped font - and the default Windows 7 fonts scales the text "over"...
    Posted to PCB Design (Forum) by N i z e on Fri, Nov 4 2011
  • [HELP] Allegro PCB file lost

    Hi guys, I just met a big problem with Allegro 16.2. I have layout all the pins on my 4-layer pcb. But I found one component had a wrong pin net name, so I updated it in Capture. After then, I re-open the .brd file and want to update the pcb, at this time, Allegro PCB design GXL pop up a warning! "WARNING...
    Posted to PCB Design (Forum) by cshinyc on Sun, Sep 11 2011
  • Automatic Router Problem- PCB Editor v16.2

    hi there, does anyone here experienced an error "Shape-Based Routing Encounetred a problem" when using Autorouter function Smart Router Strategy?... Moreover, using the Specify Routing Passes Strategy seems to work. Please advise. Thanks...thanks!
    Posted to PCB Design (Forum) by comet on Tue, Jun 14 2011
  • Extra component on board

    Hey guys, is there any basic or special way of spotting (checking) extra component/s on board?... (meaning those parts that don't really included on the design...maybe accidentally copied or placed)
    Posted to PCB Design (Forum) by comet on Mon, Apr 25 2011
  • TestPrep in OrCAD PCB Editor

    Ahoy there, I'm using OrCAD PCB Editor to create ICT testpoint. I'm trying to create a report to print net name with its associate testpoint so I can see which nets have testpont and which hasn't. How can I mark nets that already have testpoint in the DSN, so when I run testprep with "Add...
    Posted to PCB Design (Forum) by Alfandari on Wed, Apr 13 2011
  • reuse block refdes and synchronization problems

    Sorry for bothering. I encountered some problems when I work with reuse blocks. The first problem: the components inside 2 reuse blocks were assigned the same refdes, how can I change them? The second problem: the logic schematic of reuse block is not synchronized with PCB. Some signal names changed...
    Posted to PCB Design (Forum) by Samuel Zhang on Mon, Feb 21 2011
  • PCB autorouter(spectraa) not converging

    Hi, I am making my first pcb with a xilinx fpga device(256 pin BGA package).I am simply connecting the all I/O's to 4 standard 40 pin connectors.Are padstacks necessary for PCB routing??.I have drawn the schematic in Capture imported it to Layout_Plus and autorouted it. But after 3 hours of autorouting...
    Posted to PCB Design (Forum) by bennyn1 on Thu, Sep 2 2010

    We currently distribute our global library over a network folder using hard coded Enviromental Veriables. The problem is that we have no way of knowing when the library was last updated. This can cause users to be un-aware of recent library updates or if they are using old revisions of the library (due...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
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