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ISQED Keynote: How RTL Synthesis Must Change for Advanced Node Designs

Think RTL synthesis is a solved problem that needs no further discussion? Think again. In a keynote speech at the recent International Symposium on the Quality of Electronic Design ( ISQED 2013 ) Sanjiv Taneja, vice president of product engineering at the Cadence Front-End Design group, showed how advanced...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 25 2013
Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 22 2013
difference between Random Resistance faults and deterministic faults?

what is random resistance faults? how different is it from the deterministic faults? why do we do the RRFA(random resistance fault analysis)?

Posted to Logic Design (Forum) by vipul982 on Tue, Jan 15 2013
How do I insert test point in the model?

the "analyze deterministic_faults" creates a test point insertion file in .dfa format. How do I further use this file to insert the test points in the design model?

Posted to Logic Design (Forum) by vipul982 on Tue, Jan 15 2013
test procedure in Cadence encounter test tool?

How do I write a test procedure in Cadence encounter test tool?

Posted to Logic Design (Forum) by vipul982 on Thu, Jan 10 2013
Does test compaction reduces tester time or memory or both?

Does test compaction reduces tester time or memory or both?

Posted to Logic Design (Forum) by vipul982 on Wed, Jan 2 2013
Digital Logic in Analog Block – How Will You Test It?

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 10 2012
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Don’t Blow Up Your Chip on the Tester!

The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 26 2012

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ISQED Keynote: How RTL Synthesis Must Change for Advanced Node Designs

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

difference between Random Resistance faults and deterministic faults?

How do I insert test point in the model?

test procedure in Cadence encounter test tool?

Does test compaction reduces tester time or memory or both?

Digital Logic in Analog Block – How Will You Test It?

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Don’t Blow Up Your Chip on the Tester!