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  • An urgent problem with the design rule check using Assura

    When I use Assura to do the design rule check after I have done layout using the C35B4 technology in Cadence, there is always a following probleme: [1] #INFO: C35B4/C35B3 ASSURA DRC DECK(REV9 DATE 26-Apr-2011) Last modified 15-Jun-2012. does anyone know why? Thank you advance for you response.
    Posted to Custom IC Design (Forum) by UUinfini on Fri, Jun 14 2013
  • Assura: Include other files

    Hi everyone! Is it possible to split up an Assura rule file into several subfiles and include them into the main rule file which is loaded by the RSF-file? Calibre provides this feature and I really appreciate it for a clear structure. Thanks in advance! Regards!
    Posted to Custom IC Design (Forum) by PekkaH on Thu, Oct 4 2012
  • Assura41 ELW, VLW resize: CPU load 101%

    ****************************** The problem was happen after checked DRC. ********************************** The Error Layer Window and VLW keep resize. The user's CPU load on share server is 101%. ***************************************************************************************************...
    Posted to Custom IC Design (Forum) by LayMan on Tue, May 1 2012
  • Layout of Enclosed Gate Transistors (EGTs or ELTs)

    Hello, I'm designing an enclosed layout transistor but can not pass both DRC and LVS. I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura. Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly...
    Posted to Custom IC Design (Forum) by bnugent on Wed, Jun 15 2011
  • Assura 4.1 Error Report and Probing

    Hi all, Up to now I have used Assura 3.0/3.1 for LVS and I was used to use the "Error Report" for probing problematic nets and devices. In fact this worked much better for me than the LVS Debug Enviroment. Now I have my first contact with Assura 4.1 and as it seems there is not probing capability...
    Posted to Custom IC Design (Forum) by baenisch on Mon, Nov 8 2010
  • ASSURA 3.1.6 error message

    Hi, I am working with IC.5.1.4 (Cadence version 07/08) together with austriamicrosystems HitKitV3.70. I am trying to run DRC with ASSURA 3.1.6 on my layout but I get the following error message: Reading the design data... *WARNING* Inconsistent DBUPerUU in the design *WARNING* 160 is not the same as...
    Posted to Custom IC Design (Forum) by yoyega on Wed, Sep 16 2009
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