Home > Community > Tags > ASIC
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ASIC

  • Analyst's View: Electronics Among "Least Hurt" Industries

    There are some silver linings in the economic downturn that’s impacting the semiconductor industry, according to Rich Wawrzyniak, senior analyst for ASICs and SoCs at Semico . In the short video interview below, Wawrzyniak talks about his projections for semiconductor, ASIC and SoC revenues for...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 18 2009
  • Why The Reports of EDA's Demise Are Greatly Exaggerated - Part 2

    Part one of this blog looked at what I think are three questionable claims about the EDA industry – that electronics OEMs are going back to internal tool development, that foundries will buy EDA vendors, and that designers aren’t moving to lower process nodes. But whatever the truth of those...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 2 2009
  • Emulation vs. FPGA Prototyping

    There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market...
    Posted to System Design and Verification (Weblog) by Ran Avinun on Thu, Feb 19 2009
  • Build ASICs With a Strong Ecosystem: A New Paradigm

    Building ASICs is a pretty much standard process - you may define your specification based on whatever constraints you have, pick your IPs if any, do a guess-timate of your entire chip so you can figure out the budget, then commit - plunk down the cash and commit resources so you can really do the work...
    Posted to Logic Design (Weblog) by Kenneth Chang on Thu, Feb 5 2009
  • How to Make Your Chip Fail: Part II ...

    Working at Cadence for 2 years has given me a lot of experience with many different customers and their flows. It's what I looked forward to after working at 4 other companies as a designer who developed flows (since setting up an ASIC flow is fun, playing with all kinds of vendor tools (feeling...
    Posted to Logic Design (Weblog) by Kenneth Chang on Fri, Nov 14 2008
Page 3 of 3 (25 items) < Previous 1 2 3