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ASIC

The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?

The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing. The consensus is that the next growth driver is going...

Posted to System Design and Verification (Weblog) by Jack Erickson on Tue, May 14 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...

Posted to Industry Insights (Weblog) by rgoering on Fri, Mar 1 2013
TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 2 2012
Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010), we introduced the Verification Computing Platform...

Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, Feb 14 2011
User View: How Metric-Driven Verification Improves ASIC and FPGA Quality

To keep bad chips and boards from going into the field, automatic test equipment (ATE) has to be reliable. That's why Teradyne , a major ATE provider, takes verification quality very seriously. With help from Cadence, Teradyne converted from a "home grown" methodology and made the switch...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 23 2011
System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry...

Posted to System Design and Verification (Weblog) by Ran Avinun on Thu, Dec 16 2010
What Is FPGA/PCB Co-Design - And Why Is It Needed?

You may think that FPGAs are "easy" to design compared to ASICs or SoCs. But just wait until you try putting a large, complex FPGA on a printed circuit board. Several things could go wrong - including pin assignments that don't work in the board layout, signal integrity problems on the...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 5 2010
Wrapping Up 2009 With Some Reflections

As many of my customers mentioned and no surprise, 2009 was a tough year. Regardless though, designs continued to get pumped out the door by aggressive design teams, putting products in eager customer hands. I constantly get mesmerized by the number of people who are buying iPhones, including co-workers...

Posted to Logic Design (Weblog) by Kenneth Chang on Wed, Dec 23 2009
User Interview: When Formal Is Best For ASIC Verification

Formal verification can serve as the primary verification methodology for an entire ASIC if it meets the right criteria, according to Yogesh Bhagwat, technical lead at Cisco . At the recent CDNLive! Silicon Valley , Bhagwat described the verification of a DDR3 command buffer ASIC using the Cadence Incisive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 25 2009
Are SoC Development Costs Significantly Underestimated?

A stark warning about SoC development costs was sounded in a panel discussion on the “Economics of Next Generation SoCs” at the recent EE Times virtual System-on-Chip Conference . Development costs are not only high, said Ron Collett, CEO of Numetrics , but are “significantly underestimated”...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 24 2009

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ASIC

The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?

DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

TLM: The Year in Review, and Trends for 2012

Why the Demand for Acceleration and Emulation is Growing

User View: How Metric-Driven Verification Improves ASIC and FPGA Quality

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

What Is FPGA/PCB Co-Design - And Why Is It Needed?

Wrapping Up 2009 With Some Reflections

User Interview: When Formal Is Best For ASIC Verification

Are SoC Development Costs Significantly Underestimated?