Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > ASIC/Design Automation Conference
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ASIC,Design Automation Conference

  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
  • Designer View: Embedded Palladium Testbench Speeds System Bring-Up

    Emulation provides blazing fast verification speeds, but you still need a good methodology to get the most value from it. At a recorded Cadence Theater presentation at the 2013 Design Automation Conference (DAC), Mehran Ramezani, senior manager for firmware at Broadcom's Mobile and Wireless Group...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 24 2013
Page 1 of 1 (2 items)