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ARM,design rules

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...

Posted to Industry Insights (Weblog) by rgoering on Fri, Nov 2 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 8 2011
Q&A: Samsung’s Ana Hunter Offers Advance Look at 20nm

While all process node migrations have posed challenges, the move to 20nm may be more challenging than most. At this process node, lithography is so difficult that extra masks ( double patterning ) will be widely deployed. But despite the costs and challenges, the promise of higher performance and lower...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 11 2011

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ARM,design rules

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

Q&A: Samsung’s Ana Hunter Offers Advance Look at 20nm