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  • Cadence System Design and Verification at DAC 2009

    Traditionally in Cadence Marketing there were always two major events you really had to focus on: Sales Kick Off in the winter and the Design Automation Conference (DAC) in the summer. A lot has changed. Starting a few years ago, Cadence added a great deal more: webinars, seminars, segment-specific trade...
    Posted to System Design and Verification (Weblog) by Ran Avinun on Mon, Jul 6 2009
  • DAC Ecosystem Booth Panels Bring Out User Voice

    At previous Design Automation Conferences, I’ve always been most interested in what EDA users have to say. One way to hear about the user experience at this year’s DAC is to attend any of five panels at the Cadence Ecosystem Partners booth (#4200, North Hall). These panels will include representatives...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 1 2009
  • The DWARF Debugging File Format

    The Chronicles of Narnia has always been one my favorite series of books. Today, I'm not going to talk about dwarfs such as Trumpkin , the dwarf that appeared in Prince Caspian ( check out the latest movie ), but instead something called the DWARF Debugging Standard . DWARF is a file format used...
    Posted to System Design and Verification (Weblog) by jasona on Fri, Jun 12 2009
  • SystemC Interoperability - Are We There Yet?

    The biggest challenge in system-level design is modeling, and getting SystemC models to work together in simulation environments has been a long, hard struggle. Finally, it appears that the stars are aligned and we are converging on the three things we need for SystemC model interoperability –...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 19 2009
  • ARM libraries, IBM PDK, Cadence PVS questions...

    Hi all, I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS. Sorry if I posted in the wrong place ARM Libraries 1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool IBK PDK 1. After I installed it, I got the following warning message in Virtuoso CIW...
    Posted to Custom IC Design (Forum) by weiz on Wed, Apr 29 2009
  • Embedded Software Providers Confront Low Power Design

    I’ve had a nagging question at the last few Embedded Systems Conferences I’ve attended. Why isn’t anyone here – aside from a few silicon vendors – talking about low power design? If you go to any hardware design conference, low-power design will be a major theme, if not...
    Posted to Industry Insights (Weblog) by rgoering on Fri, Apr 3 2009
  • When Do You Know You've Saved Enough Power?

    This guest post is by David Weir, Lead Design Engineer at Cadence. His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley. In this paper we set out to show how designers can measure and explore the impact of implementing...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 2 2009
  • Software Verification or Validation With ISX?

    [Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.] At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title " Metric Driven Functional Verification of Embedded...
    Posted to System Design and Verification (Weblog) by TeamESL on Mon, Mar 30 2009
  • Design Metrics - ARM is Onto Something

    We here at the Logic Design blog seem fascinated with improving design metrics . Why is that? Perhaps we've seen too many designs go through "long loop" iterations later in the cycle because improper metrics were used to determine the design's "goodness" early in the cycle...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Feb 23 2009
  • Exploring the Virtual Platform Part 4

    Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1 , Part 2 , and Part 3 of the series to get up to speed (hopefully soon before it becomes too difficult for me to provide links to every previous topic and too difficult for you...
    Posted to System Design and Verification (Weblog) by jasona on Fri, Feb 13 2009
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