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ARM Techcon,Industry Insights
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Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Nov 2 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 31 2012
Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More
With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 23 2012
Interconnect Workbench Eases Analysis and Verification for ARM-Based SoCs
In today's complex SoCs, early performance analysis and verification of SoC interconnect is crucial. Architects must ensure that interconnect will meet the bandwidth and latency requirements of the target application, while verification engineers must build a testbench that assures functional correctness...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 9 2012
ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout
In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Dec 8 2011
ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow
You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 30 2011
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 21 2011
ARM TechCon Paper: Why DRAM Latency is Getting Worse
There's a general view that everything gets faster and better as technology advances, but when it comes to external memory latency, that's not the case. In a recent ARM TechCon paper Marc Greenberg, director of product marketing at Cadence, showed why DRAM latency is increasing and discussed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 17 2011
ARM TechCon Paper: New Methodology Eases Challenges of 32/28nm Designs
The 32nm and 28nm process nodes, the most advanced nodes currently in production, pose formidable challenges in complexity, power management, variability, and manufacturability. A recent ARM TechCon paper authored by Cadence and Samsung described a methodology that can resolve those challenges. And it's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 9 2011
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