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AMS simulation,verilog

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  • Simulating verilog using cadence

    Hi! I am new to this forum so please bear with me if my question is basic, anyways here goes. I am trying to simulate a state machine (kind of) in cadence using the ams simulator. NOw I have tested and verified that the design works using model sim. When I try to simulate it using the ams simulator the...
    Posted to Logic Design (Forum) by MTP3 on Fri, May 11 2012
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