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CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification
With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance...
Posted to
Mixed-Signal Design
(Weblog)
by
AElzeftawi
on Mon, Apr 9 2012
Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley
With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Wed, Mar 7 2012
Virtuoso AMS Designer Wins the China ACE Best EDA Product Award
The China Annual Creativity in Electronics (ACE) Awards was established to recognize individuals, companies and technologies that have made profound impacts in the overall China electronics industry each year. Joining with the industry prestigious names like ARM and TI, Cadence Virtuoso AMS Designer...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Tue, Feb 28 2012
Webinar Report: Power-Aware Mixed-Signal Verification
Most of the discussion about low-power design techniques has focused on digital circuits. However, nearly all systems-on-chip (SoCs) are mixed-signal, and the way in which analog and digital circuitry interact has a huge impact on overall power consumption. Thus, low power (or "power aware"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 25 2012
Webinar Report – New Approaches to Mixed-Signal Verification and Assertions
Nearly all systems-on-chip (SoCs) are mixed-signal, and as complexity grows, new verification techniques are needed. No longer is it sufficient to use traditional analog and digital simulation in isolation - instead, information must flow freely between analog and digital domains to allow a true mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 19 2012
DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs
Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
Analog/Mixed-Signal Behavioral Modeling – When to Use What
Mixed-signal verification is a tough challenge, and much of the difficulty lies with models. How can engineers choose the right modeling approach and guarantee that models accurately represent the silicon? A session at last week's (Feb. 17) Cadence "Tech on Tour" seminar provided some answers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Feb 20 2011
Users Outline New Approaches To Mixed-Signal Verification
At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 2 2009
Let’s Bring Analog Into Low-Power Design Discussion
The discussion about low-power IC design has been focused on digital implementation from RTL on down. We are beginning to move above RTL with tools and methodologies that consider power at a systems level. But what’s not so often discussed is the use of low-power design in mixed digital and analog...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Sep 11 2009
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