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AMD

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit acceleration capabilities to our System Development...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, May 16 2012
Panel: Is the Cloud the Solution to IC Design Collaboration?

Semiconductor design increasingly requires collaboration by geographically-dispersed design teams, as well as partners and third-party suppliers. Private or public cloud computing may provide a rich environment for this collaboration, but some key questions and challenges remain, according to panelists...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 20 2011
Panelists Broaden Scope Of Low-Power Discussion

Most of the discussion about low-power design has centered around the RTL-to-GDSII flow for digital ICs. But the real problem is much broader, according to panelists from AMD , Sonics , Wipro , and Cadence at the recent Power Forward Initiative (PFI) Low-Power Design Summit Oct. 20. Entitled “The...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 26 2009
User Interview: What to Expect At 32 nm and Below

Norma Rodriguez, senior member of technical staff at AMD , has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted layout patterns as well as DFM tools. At the...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 26 2009
Advanced Node Panel: Making The Case For Restricted Design Rules

You would think that designers would not welcome restrictions on what they do, but panelists at the recent Design Automation Conference saw restricted design rules (RDRs) as a helpful and necessary step towards 32 nm/28 nm IC design. Panelists from AMD , TSMC , Texas Instruments , and Cadence spoke Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 6 2009
Expect the Unexpected - Using MSV Beyond MSV

I was just reading Rich Owen's post, "What I am Thankful for - The Geek Version" , and I cannot agree more on the creative and sometimes utterly crazy uses of technology that users find. More often than one would guess we ran into users who are trying some truly unexpected uses of technology...

Posted to Logic Design (Weblog) by grasshopper on Mon, Dec 1 2008

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AMD

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

Panel: Is the Cloud the Solution to IC Design Collaboration?

Panelists Broaden Scope Of Low-Power Discussion

User Interview: What to Expect At 32 nm and Below

Advanced Node Panel: Making The Case For Restricted Design Rules

Expect the Unexpected - Using MSV Beyond MSV