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ADEGXL

  • *Error* times: can't handle (3.0 * nil)

    I've been using the ADE-GXL optimization features on resistors and getting good results. I’ve now move to trying FETs and I’m getting some strange behavior. I'm using the optimizer to select the number of fingers for some FETs. If I set the finger parameters to be scale up to 5 (1...
    Posted to Custom IC Design (Forum) by BradW on Thu, Oct 25 2012
  • How to enforce the order of simulations in ADE GXL?

    Dear Community, I am trying to optimize the propagation delay of a comparator using ADE GXL. The propagation delay of the comparator is characterized using a transient simulation, but I also need to run a DC analysis to compute the actual threshold voltage when the parameter values of the circuit (e...
    Posted to Custom IC Design (Forum) by tribeca on Wed, Sep 26 2012
  • AMS simulator error

    Hi, I'm using CADENCE Virtuoso ADE 6.1.3 for mixed simulation. I have to simulate schematic block which is driven by digital pins (clk, rst, ...). I set up a config view using AMS simulator and when I run a simulation I got the following error message in my irun.log : Elaborating the design hierarchy...
    Posted to Custom IC Design (Forum) by inessadm on Tue, Sep 11 2012
  • ADE results display issue over ssh+x forwarding

    Hi, I have a problem plotting simulation results in ADE GXL when accessing Cadence on a remote computer via ssh with X forwarding. My simulations run OK, but when I plot the results a blank graph window appears and then my local X session freezes. I can't alt-ctrl-backspace or alt-ctrl-f2 out and...
    Posted to Custom IC Design (Forum) by ajc4000 on Fri, Jul 6 2012
  • Virtuoso ADEGXL: SKILL function falltime(...)

    Hello Virtuoso SKILL Programmers, I m using the ADEGXL for measuring delay, power, slewrate of some digital blocks like NAND2 NOR2 a.s.o. As it is described in the Manual of the SKILL function fallTime, it can be applied e.g.: wavelet=fallTime(v("/Y" ?result "tran-tran") 0.9 nil 0...
    Posted to Custom IC Design (Forum) by Eberhard2010 on Tue, Apr 17 2012
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • Save and Check in IC61

    H,there I am using IC614 and mmsim72.When I finish a schematic and press x,then lunch ADEGXL and press run,it inform me of this schematic is not save and want me to press "Save and Check" button.I used IC5141 before and I can run the simulation only press x to check,not save. Must I save before...
    Posted to Custom IC Design (Forum) by minci on Wed, Dec 15 2010
  • Monte Carlo Analysis | HitKit

    Hi, I was trying to perform a statistical analysis, but encountered some problems: 1) According to this tutorial : http://asic.austriamicrosystems.com/hitkit/circuit_sim/montecarlo/monte_spectre.html I am supposed to to open Tools -> Monte Carlo in ADE window. Unfotunatelly there is no 'Monte...
    Posted to Custom IC Design (Forum) by pitter on Sat, May 8 2010
  • how to create link between new MMSIM and ADEGXL in IC610

    hi I am having trouble in linking MMSIM and ADEGXL. When I try to run simulation in ADEGXL then it shows me the error “ ADEXL-1613: Following tests use older version of Spectre: sensor: inverter_new:1. Make sure to use MMSIM60 or above for these tests”. So I installed newer version of MMSIM...
    Posted to Custom IC Design (Forum) by ashraf on Tue, Jul 29 2008
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