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ADEGXL,AMS virtuoso simulation

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  • AMS simulator error

    Hi, I'm using CADENCE Virtuoso ADE 6.1.3 for mixed simulation. I have to simulate schematic block which is driven by digital pins (clk, rst, ...). I set up a config view using AMS simulator and when I run a simulation I got the following error message in my irun.log : Elaborating the design hierarchy...
    Posted to Custom IC Design (Forum) by inessadm on Tue, Sep 11 2012
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