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ADE,netlist

  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • Parametric analysis - voltage error in the netlist

    I found that when I run parametric sweep with fine voltage step, netlists are sometimes generated with wrong value. For example, when I run parametric analysis with the voltage changing from 0 to 1V with 1/2560V(=390.625uV) step, 62.5mV is changed to 62.4999999999998V in the netlist. Is there some kind...
    Posted to Custom IC Design (Forum) by Seokhyun Jeong on Mon, Apr 28 2014
  • Need to place a pin on the symbol for an internal VerilogA signal

    I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal. So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic...
    Posted to Custom IC Design (Forum) by boast on Tue, May 7 2013
  • how to load ADE state in skill?

    Hello I need to create a netlist for a testbench cellview, in batch mode. Basically I want to have in the skill script smthing like: mysession = asiCreateSession(?simulator "spectre" ?lib LIB ?cell CELL ?view VIEW ?mode 'r') asiLoadState(mysession ?name "spectre_state1" ?option...
    Posted to Custom IC Design (Forum) by LarissaN on Wed, Jun 15 2011
  • ams: simulating design with spice netlist with bus ports

    I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really...
    Posted to Custom IC Design (Forum) by Runner on Mon, Sep 14 2009
  • Error in Virtuoso..

    Hi all.. I got this error while designing, I have never encountered it before. Can anyone help me ? Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libphilips_sh...
    Posted to Custom IC Design (Forum) by kgulur on Sat, Sep 27 2008
  • Virtuoso ADE bug: netlist regenerated even when clicking yellow light

    Whenever I click the yellow light (the run button) and NOT the green light (netlist and run), a new netlist is generated anyway. Is this a bug? Is there some setting that I should change to stop this from happening? Thanks, Daisy
    Posted to Custom IC Design (Forum) by Heartilly2000 on Tue, Aug 12 2008
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