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  • .csv output in Spectre

    What is the easiest way to generate .csv format output in Spectre?
    Posted to Custom IC Design (Forum) by dmckenney on Thu, Dec 3 2009
  • Transient Noise Analysis | Noise File

    Hello, I am going to measure jitter of a VCO by means of Transient Noise Analysis. Simulation setup is not sophisticated, but I have some general questions though. I am using models of transistors that have been provided by PDK and they contain noise model too? In model setup dialog box (ADE) I can choose...
    Posted to Custom IC Design (Forum) by pitter on Wed, Nov 18 2009
  • asiAddSimOption question

    Hey, Does any one have experience with using the asiAddSimOption method. More precisely, I would like to use the ?editable field. My understanding is that each time the user click in the simulator option, the expression is evaluated. It the evaluated expression is true, then the sim option...
    Posted to Custom IC SKILL (Forum) by polo on Thu, Nov 12 2009
  • Transient Difference Plots unable to refresh

    Hi, Currently, I encountered some problems when using IC 6.1.3, specifically the calculator functions - Logic Operations. After the first run of simulation, it seems as if memory registers used in Logic Operations such as subtraction (essential for differential signals) were logged and unable to clear...
    Posted to Custom IC Design (Forum) by Harloeworld on Mon, Nov 9 2009
  • ADE L | post-layout simulation | input.scs error | missing model

    Hi, after successful RLC extraction I got a av_extracted view, which I set in ADE Setup->Environment... in the Switch View List in order to perform post-layout simulation. The netlist is created without any error. However, when I start to run a transient simulation I get te following error: <<...
    Posted to Custom IC Design (Forum) by pitter on Sat, Nov 7 2009
  • Weird plotting problem in ADE

    Hi, I am running a transient sim. After running a simulation for a certain amount of time, when I try to plot a node, it gives me a blank plot with a small dot at t=0. The time scale is -1 to 1 seconds. Zooming to the point doesn't show anything. Has anyone else encountered the problem? Is it something...
    Posted to Custom IC Design (Forum) by mk123 on Tue, Nov 3 2009
  • Users Outline New Approaches To Mixed-Signal Verification

    At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 2 2009
  • ams: simulating design with spice netlist with bus ports

    I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really...
    Posted to Custom IC Design (Forum) by Runner on Mon, Sep 14 2009
  • Problem with Simulating Design using Spectre

    I have created a schematic using Virtuoso 6. When I open the ADE, it says "(deLicense-7) Could not get a license for ADE L. Would you like to try to get a higher-tiered license to run this product?" When I click on Yes, it starts the ADE, but when I set up the analysis and click on "Netlist...
    Posted to Custom IC Design (Forum) by govilv on Thu, Jun 4 2009
  • VerilogA Problem in MMSIM-7.1

    Hi, I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get: ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi...
    Posted to Custom IC Design (Forum) by gokce on Wed, Jun 3 2009
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