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ADE

  • How to easily update ADE/ADE-XL testbenches with new model files?

    Hello, I just wanted to ask if there is any easy way of updating the model files in all my saved state files (ADE-L) and my ADE-XL testbenches. We recently updated the model files that we are using and the latest files now reside in a different directory. I was wondering if there is any automatic or...
    Posted to Custom IC Design (Forum) by D L on Tue, Jul 22 2014
  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • Tutorial for absolut beginners on schematic and ADE.

    Hello! Where can I find a kind of tutorial for absolut novice on Cadence 6.15 Virtuoso Schematic and ADE (e.g. step-by-step description how to draw simple schematic and simulate it)? Does Cadence provide such kind of documentation? Thank you in advance
    Posted to Custom IC Design (Forum) by Runner on Tue, Jul 15 2014
  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • ADExl problem with bus notation

    Running a spectre simulation from adexl I am getting this error: Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 3633: Unexpected operator ">". Expected end of file or end of line. The interesting part of scs netlist is listed below. Please note that...
    Posted to Custom IC Design (Forum) by sram8t on Mon, Jun 16 2014
  • Modify ADE Toolbar buttons

    Hi, Is it possible to modify the ADE toolbars in virtuoso 6.1 ? There is a directory located at 06.15.511/share/cdssetup/dfII/toolbars/byApplication" which gives the templates for the toolbars for all of the other tools (including ADEXL, ADEGXL, schematic, symbol, analogArtist_schematic), but I...
    Posted to Custom IC SKILL (Forum) by NiallDuncan on Fri, Jun 6 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • ADE window opens on opposite display

    Hi, I use Cygwin's X Server to access Cadence ADE L running on a linux machine. On my client there are 2 displays: 1 secondary (auxiliary) one to the left and a primary, main monitor on the right. Whenever ADE opens a new window, the new window appears always on the secondary monitor, in particular...
    Posted to Mixed-Signal Design (Forum) by itos on Mon, May 5 2014
  • ADE ~> Outputs to be saved

    Dear all, I have question about how ADE managing its outputed node/pins. I open ADE -> Outputs -> To be saved -> Select On Schematic I have selected the pin on an Instance from schematic. similar below: I44/vout1 I44/vin2p Then I go to Simulation -> Netlist -> Create The value under save...
    Posted to Custom IC SKILL (Forum) by Kai1646 on Thu, May 1 2014
  • Parametric analysis - voltage error in the netlist

    I found that when I run parametric sweep with fine voltage step, netlists are sometimes generated with wrong value. For example, when I run parametric analysis with the voltage changing from 0 to 1V with 1/2560V(=390.625uV) step, 62.5mV is changed to 62.4999999999998V in the netlist. Is there some kind...
    Posted to Custom IC Design (Forum) by Seokhyun Jeong on Mon, Apr 28 2014
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