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ADE,IC610

  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • ADE hangs up when java is running

    Dear Cadence-Experts, I have a problem with the ADE (Analog Design Environment) running within a newly installed Cadence software (IC 6.1.3, MMSIM 7.01, IUS 8.10 under RedHat 4 on Intel Core i7 CPU 950). Problem scenario 1: * A quick way to trigger the problem is to try to change the "Project Directory"...
    Posted to Custom IC Design (Forum) by Michael2010 on Thu, Nov 25 2010
  • ADE L 6.1.4 Parametric/MonteCarlo Sweep

    I will soon help with evaluation of the 6.1 version of cadence. To maximize the time I have for evaluation, I have some general questions. In the new version, the model sections can be set with a design variable using VAR. From reading the manuals, a few of things are not clear to me: 1) Can this design...
    Posted to Custom IC Design (Forum) by MarkSummers on Sun, Jun 27 2010
  • Problem with Simulating Design using Spectre

    I have created a schematic using Virtuoso 6. When I open the ADE, it says "(deLicense-7) Could not get a license for ADE L. Would you like to try to get a higher-tiered license to run this product?" When I click on Yes, it starts the ADE, but when I set up the analysis and click on "Netlist...
    Posted to Custom IC Design (Forum) by govilv on Thu, Jun 4 2009
  • VerilogA Problem in MMSIM-7.1

    Hi, I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get: ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi...
    Posted to Custom IC Design (Forum) by gokce on Wed, Jun 3 2009
  • Error in Virtuoso..

    Hi all.. I got this error while designing, I have never encountered it before. Can anyone help me ? Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ... Loading /opt/cadence/IC5141/tools.lnx86/cmi/lib/4.0/libphilips_sh...
    Posted to Custom IC Design (Forum) by kgulur on Sat, Sep 27 2008
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