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ADE,Analog artist

  • IC5141 ADE scalar results

    Hi, It's there a way to change the format of the scalar results printed in ADE window ? By default it has only 4 numbers, for example 45.78m . I want to be printed as 45.789244m . What should I put in .cdsinit or .cdsenv to change this number format ?? It is possible to print this results in the...
    Posted to Custom IC Design (Forum) by DanySF on Tue, Jul 5 2011
  • Have device connectivity added as an include?

    Hi, Presently, the device connectivity portion of the input file is added as a "cat" function where every single line of the device connectivity shows up as a line in the input file. Is there any hidden switch to change the behavior so that the device connectivity shows up as a single .include...
    Posted to Custom IC Design (Forum) by SharksFan on Fri, Aug 13 2010
  • Monte Carlo Analysis | HitKit

    Hi, I was trying to perform a statistical analysis, but encountered some problems: 1) According to this tutorial : http://asic.austriamicrosystems.com/hitkit/circuit_sim/montecarlo/monte_spectre.html I am supposed to to open Tools -> Monte Carlo in ADE window. Unfotunatelly there is no 'Monte...
    Posted to Custom IC Design (Forum) by pitter on Sat, May 8 2010
  • Tcl Commands to set method of Integration

    Dear All, I am new to this community. Let me introduce as Debjit from India. I am facing the following problem. I want to change the method of integration and/or the errpreset of a simulation during run time. I am able to change the reltol, vabstol, iabstol value during runtime by tcl commands like "analog...
    Posted to Custom IC Design (Forum) by mobileee on Wed, Apr 7 2010
  • About the spectre pss problem

    Hi, deal all: I use the old version of spectre (ver 5.10.41), when I do a vco pss analysis , I found the spectre can't catch the frequency of the vco. For example , before the pss analysis a run a tran analysis. measure the freq=1.4617G(when the vco have reach the stable state);but in the following...
    Posted to Custom IC Design (Forum) by kivvzhou on Mon, Mar 15 2010
  • VerilogA Problem in MMSIM-7.1

    Hi, I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get: ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi...
    Posted to Custom IC Design (Forum) by gokce on Wed, Jun 3 2009
  • AEL expression in CDF

    Hi, I'm trying to modify a resistor value in its CDF via an conditional expression as below (iPar("b1")==1) ? iPar("p3") : iPar("p4") where b1, p3 and p4 are previously defined in the CDF. The AEL reference document lists "?:" as a valid operator. But it doesn't...
    Posted to Custom IC Design (Forum) by hkutuk on Thu, Jan 22 2009
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