Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > ADE/ADE ADEXL
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ADE,ADE ADEXL

  • How to easily update ADE/ADE-XL testbenches with new model files?

    Hello, I just wanted to ask if there is any easy way of updating the model files in all my saved state files (ADE-L) and my ADE-XL testbenches. We recently updated the model files that we are using and the latest files now reside in a different directory. I was wondering if there is any automatic or...
    Posted to Custom IC Design (Forum) by D L on Tue, Jul 22 2014
  • ADExl problem with bus notation

    Running a spectre simulation from adexl I am getting this error: Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 3633: Unexpected operator ">". Expected end of file or end of line. The interesting part of scs netlist is listed below. Please note that...
    Posted to Custom IC Design (Forum) by sram8t on Mon, Jun 16 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • Problem in running tests with different stimulus together in ADE XL

    I am simulating an opamp in ADE XL. I am using differential stimulus to get differential gain in one test & common mode input stimulus for common mode gain in another test. The inputs are provided through user defined stimulus files.When I run these tests together in ADE XL I get an erroneous output...
    Posted to Custom IC Design (Forum) by Parameswaran on Tue, Jun 4 2013
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • TFT and BSIM device equations

    Hello everyone I am working TFT circuit design. According to Virtuoso® Simulator Circuit Components and Device Models Manual Product Version 7.1.1 June 2009, Cadence Spectre and UltraSim simulators support RPI TFT model. The equations of RPI TFT models are listed in the above file. I created the...
    Posted to Custom IC Design (Forum) by SilentHunter on Sat, May 14 2011
  • Plotting new post-simulation outputs in ADEXL

    Hi, I'm using IC6.1.3.500.11. I have a pretty simple problem which I can't seem to find the solution to. After finishing a simulation in ADE XL and changing or adding some expressions in my 'Outputs Setup' window, the new expressions are not reflected in the 'Results' tab. It...
    Posted to Custom IC Design (Forum) by blorbx on Wed, May 11 2011
  • Re: setup Distibuted processing in ADE L

    Hi Andrew, thinks for your help. I'm only set LBS_BASE_SYSTEM LBS_SGE in .cshrc ERROR (33) : A connection could not be established to the LBS queue Please help me agen that how to configure DP in ADE L whith LSF or SGE Please write carefully
    Posted to Custom IC Design (Forum) by edafans on Mon, Apr 11 2011
Page 1 of 1 (8 items)