Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> ADE-XL
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
ADE-XL
20nm
28nm
45nm
ADE
ADE XL
ADE-GXL
ADEnalog
advanced node
AMS
AMS Simulation
Analog
Analog Design Environment
Analog Design Environment
Analog simulation
APS
Bleasdale
Cadence Space-based Router
calibration
change
Circuit Design
Constraint-driven
corner analysis
corners
Corners analysis
custom design
Custom IC Design
custom/analog
delay
drag and drop
Encounter
IC 6.1
IC 6.1.4
IC 6.1.5
IC6.1.5
IC615
Industry Insights
interoperability
Jupalli
mixed signal
mixed-signal
modgens
Monte Carlo
OCEAN
OCEAN-XL
optimization
PAD
Parasitic analysis
parasitic-aware design
parasitics
PVT
RAKs
Rapid Adoption Kit
runICRP
Schematic Editor
sensitivity analysis
setup states
Simulation
SKILL
SKILL++
slow
Spectre
statistical analysis
statistical corners
statistical models
variability
Variability Aware Design
variation
variation analysis
variation-aware
Virtuosity
Virtuoso
Virtuoso Advanced Node
Virtuoso Analog Design Environment
VIrtuoso drag and drop
Virtuoso IC 6.1.3
Virtuoso IC6.1.5
Virtuoso Layout Suite
Virtuoso Layout Suite GXL
Virtuoso Layout Suite L
Virtuoso Layout Suite XL
Virtuoso Space-based Router
Viva
ViVa-XL
VLS GXL
VLS L
VLS XL
VSR
webinar:
Whiteman
workshop
worst case corners
wreal
Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support
Topics in March include advanced analysis in ADE GXL, taking advantage of lots of features for doing statistical analysis in ADE XL, defining bindkeys in ADE L (yes, you can do that!), plus a variety of useful details in the areas of routing and advanced custom layout. Enjoy! Application Notes 1. Design...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 11 2013
Virtuosity: 10 Things I Learned in February By Browsing Cadence Online Support
February was a big month for RAKs (Rapid Adoption Kits)! If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out. You'll find databases with detailed instructions, documentation and videos on many tools, features and flows. They've become...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, Mar 18 2013
Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support
This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more. Enjoy and don't forget to leave feedback at the top of the individual content pages...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Fri, Feb 15 2013
Things You Didn't Know About Virtuoso: Drag and Drop
I love it when I'm sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says "Wait, why are you doing it that way? Why don't you just...". Immediately my mind says "blog...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Wed, Feb 13 2013
Is there a way to recover an adexl view that's missing its data.sdb file?
I created an adexl view, ran simulations, saved and closed it. Accidentally my virtuoso session crashed for some reason and the next time I restarted virtuoso, I can't open the adexl view I had previously saved. I looked at the unix directory and the data.sdb file for that adexl view had gotten deleted...
Posted to
Custom IC Design
(Forum)
by
123deepa
on Tue, Jan 15 2013
Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support
In addition to the R&D engineers who actually develop our software, the folks in many other groups here at Cadence put a lot of time and effort into creating a wide variety of documents, presentation and videos to help our users learn to use the software more effectively. Today we're kicking...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, Jan 14 2013
delay in simulation initialization in ADE-XL
Hi Andrew, We have a small but aggravating issue in running simulations on ADE-XL with IC6.1.5/MMSIM 10.11 When we run a simulation by pressing the green "play" button in the old fashioned test editor (opened from ADE-XL), the simulation starts to run instantly, as expected. But when we run...
Posted to
Custom IC Design
(Forum)
by
aditeman
on Wed, Nov 28 2012
Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Nov 11 2012
Things You Didn't Know About Virtuoso: The (Setup) State of Things
Apologies for the long delay between articles (best intentions and all that). I last left you with an article about how to parameterize and manipulate device properties in your design without having to edit the schematic. A very handy feature. So there you are -- creating and matching and ratioing parameters...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Wed, Sep 5 2012
Things You Didn't Know About Virtuoso: Change is Here to Stay
Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis. After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Thu, Apr 5 2012
Page 1 of 3 (27 items) 1
2
3
Next >