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ADE "Model Setup"

  • ADExl problem with bus notation

    Running a spectre simulation from adexl I am getting this error: Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 3633: Unexpected operator ">". Expected end of file or end of line. The interesting part of scs netlist is listed below. Please note that...
    Posted to Custom IC Design (Forum) by sram8t on Mon, Jun 16 2014
  • Re: Extracted simulation ERROR (SFE-23): "input.scs" 17: c1 is an instance of an undefined model cmodel.

    Hi Andrew, You have told to set to "Include Model" on the QRC extraction form --> Netlisting tab to overcome the "recursive include error". How do I get to QRC Extraction form? Where can I find this ? Can you please let me know in detail. The error I am getting is "Recursive...
    Posted to Custom IC Design (Forum) by KR1089 on Sat, Apr 20 2013
  • ADEL check model files and paths

    Hello, I would like to create a trigger that checks my model libraries and paths when I run a simulation. It would check the model paths as well as the model files. If they are not set to the EDA defaults, I would like a dialog box to come up warning me that I am simulating with a non-standard set of...
    Posted to Custom IC Design (Forum) by acook on Wed, Mar 27 2013
  • Aging simulation with RelXpert and Eldo

    Hello everyone I would like to simulate the aging behavior on circuit-level of the circuits built by bulk-Si CMOS technology. I know that there is a tool named “RelXpert” (combined with UltraSim) in Analog Design Environment (ADE) of Cadence Virtuoso can be used for aging (NBTI and HCI) simulation...
    Posted to Custom IC Design (Forum) by SilentHunter on Sun, May 15 2011
  • How to change save state default setup?

    Hi, I'd like to change the default configuration when saving state in ADE (L): I want to uncheck "Model Setup". I can't find the corresponding environment variable to set (asimenv something I guess). I tried a CIW->Options->Save Defaults without success. Anyone have a suggestion...
    Posted to Custom IC Design (Forum) by SebV on Tue, Dec 21 2010
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