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ADE XL,mixed-signal verification

  • bus value export to table

    I am working on an ADC. I would like to be able to export the value of the output bus to a table. Basically I have an n-bit hexadecimal bus and a trigger signal. I am using Visualization & Analysis XL. I would like to have a table on the screen or a file that reports the value of the bus on the falling...
    Posted to Mixed-Signal Design (Forum) by Bob Mounger on Fri, Aug 22 2014
  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • How to store the description or the condition of a specification of a design in ADE-XL

    Hi, I am wondering how could I store the description or the condition of a specification of a design in ADE-XL? Is that possible to customize the "Outputs Setup" tab of the main ADE XL canvas so that I can add a new column to store the condition? Thanks, hpan
    Posted to Mixed-Signal Design (Forum) by hapn on Mon, Nov 11 2013
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