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  • Re: mixed signal simulation

    thanks for your valuable guidance.... sir, in my project i have designed one block in verilog.Now i need to integrate it to the remaining analog blocks. so i generate verilog netlist of the corresponding digital block. But after integrating it with analog block i need to check functional and transistor...
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Thu, Jul 17 2014
  • mixed signal simulation

    is it possible to simulate verilog netlist in cadence virtuoso?how to bind the standard netlist cell to the corresponding code?
    Posted to Mixed-Signal Design (Forum) by KUMARJAYA on Wed, Jul 9 2014
  • Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support

    Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides and FAQs. Application Notes 1. Using Annotation Browser with Virtuoso IPVS Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the...
    Posted to Custom IC Design (Weblog) by stacyw on Thu, May 22 2014
  • Monte Carlo AMS Simulation with ADE-XL not working properly

    Hi everybody, I'd really appreciate if any of you could help me concerning following problem i'm facing using ADE-XL. I designed a mixed signal circuit and I'd like to estimate the effect of mismatch on my analog part while using the functional view of the standard digital cells I used to...
    Posted to Mixed-Signal Design (Forum) by GabrielB on Wed, Oct 23 2013
  • Circuit Regression Flow

    I'm trying to define a circuit regression flow. From what I learned, there seems to be 2 options. I haven't looked too deep into either one. But I'd like to solicit some inputs first. General Background * analog and mixed signal IP; roughly half circuit, half logic. * logic verification with...
    Posted to Custom IC Design (Forum) by Jacck on Fri, Nov 5 2010
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