Home > Community > Tags > ADE ADEXL
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

ADE ADEXL

  • Run ADE XL with ocean scripts

    Hello, I'm trying to run a Custom Analysis running MPP2 with an ocean script but I have the error : ERROR (ADEXL-1529): No samples specified for the test 'work_Mohamed:ampdiff1:1'. Specify the samples for this test and then run the simulation. ERROR (ADEXL-1600): Cannot find an active session...
    Posted to Custom IC Design (Forum) by Mohsashi on Mon, Aug 18 2014
  • How to easily update ADE/ADE-XL testbenches with new model files?

    Hello, I just wanted to ask if there is any easy way of updating the model files in all my saved state files (ADE-L) and my ADE-XL testbenches. We recently updated the model files that we are using and the latest files now reside in a different directory. I was wondering if there is any automatic or...
    Posted to Custom IC Design (Forum) by D L on Tue, Jul 22 2014
  • ADExl problem with bus notation

    Running a spectre simulation from adexl I am getting this error: Error found by spectre during circuit read-in. ERROR (SFE-874): "input.scs" 3633: Unexpected operator ">". Expected end of file or end of line. The interesting part of scs netlist is listed below. Please note that...
    Posted to Custom IC Design (Forum) by sram8t on Mon, Jun 16 2014
  • Help with complete understanding of "vsin" source in Cadence

    Hi. I kind of thoroughly Googled before posting this question for seeking help from you guys! The "vsin" source (in analogLib) of Cadence has many parameters: i) AC magnitude, AC phase, DC voltage ii) Offset voltage, Amplitude, Frequency,... Question 1: Internet resources are indicating that...
    Posted to Custom IC Design (Forum) by jdp721 on Sun, May 11 2014
  • stb simulated results different in ADE-L and ADE-XL

    hi,everyone, I am simulate a crystal osc ,which main circuit is just a simple nmos with it's drain connected to gate through a resistor.And I put a zero vdc at the drain to do stb analysis.It's oscillate frequency is 25M ,so i choose frequency from 24M to 26M ,linear step ,every step is 100....
    Posted to Custom IC Design (Forum) by xianweng on Tue, Apr 22 2014
  • how to list all devices and their operating region in a file

    Hello, is it possible in ADEXL to list all devices and their operating region in a file? I am not talking about a particular device, I have hundreds, and just want check all what regions they are in. I couldn't find circuit conditions ADEX. thanks
    Posted to Custom IC Design (Forum) by kxlux on Fri, Aug 30 2013
  • a strange phenomena about ade and ade xl

    Hi,all I can not plot loop gain and loop phase after finished stb analysis in ade! The window show nothing. But waiting about 5 minutes,I can plot them. I can not plot tran wave after finished tran analysis across different corner! The window show noting.But waiting about 5 minutes,I can plot them. It...
    Posted to Custom IC Design (Forum) by xianweng on Mon, Aug 5 2013
  • Problem in running tests with different stimulus together in ADE XL

    I am simulating an opamp in ADE XL. I am using differential stimulus to get differential gain in one test & common mode input stimulus for common mode gain in another test. The inputs are provided through user defined stimulus files.When I run these tests together in ADE XL I get an erroneous output...
    Posted to Custom IC Design (Forum) by Parameswaran on Tue, Jun 4 2013
  • Pnoise analysis

    Hi, I have been doing a pnoise analysis for a PLL . Looking into the Pnoise simulation profile I have found a tab regarding thevalue for " Reference sideband" .What is the value that I should put while my "Maximum number of sidebands =7". With Regards, Jithin K
    Posted to Custom IC Design (Forum) by Jithin on Wed, Apr 3 2013
  • ADEXL: Plot vs save

    Hi, Why can you check plot and not check save in ADEXL? Shouldn't it be automatically saved when you plot? If this is the case, the save checkbox should be automatically checked and/or disabled. Or have I misunderstood the meaning of plot vs save?
    Posted to Custom IC Design (Forum) by Tobben24 on Fri, Nov 30 2012
Page 1 of 2 (20 items) 1 2 Next >