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ADE XL

  • Phase noise plot

    Hi, I have been doing a Pnoise analysis . Unfortunately I was unable to plot the phase noise response. My design was setup was described below. My apparatus was a PLL with a fixed divider ratio of 20 and output frequency of 500Mz In PSS analysis I have set the beat frequency as reference frequency ie...
    Posted to Custom IC Design (Forum) by Jithin on Wed, Apr 10 2013
  • ADE XL multiple tests with different corners

    Nevermind... I can that which tests that should be run can be selected when defining corners. --------------------------------------------------------------------------------- Hi, If you have multiple test in ADE XL, can you define which corners that should be runned individually for each test? Or does...
    Posted to Custom IC Design (Forum) by Tobben24 on Wed, Mar 20 2013
  • Operating Region Spec

    Hi, I'm trying to add a Op Region Spec from Outputs Setup tab in ADE XL. When I try to add a new output which is op region spec, I was transfered to the schematic, but the operating assistant is no opened. I see a error in the CIW: hiMapWindow: argument #1 should be a window type ( type template...
    Posted to Custom IC Design (Forum) by Tobben24 on Wed, Mar 20 2013
  • ADEXL and VerilogA

    Hi, Is it possible to control variables defined in a veriloga symbol from adexl as a normal parameter?
    Posted to Custom IC Design (Forum) by Tobben24 on Tue, Mar 19 2013
  • ADE XL Dynamic Spec

    Hi, Is it possible to create a spec for a test signal that is dynamic? Say you have a requirement to a signal that is based on what your supply is, ie. the output should be < Vdd*0.7. I have been able to achieve this by creating a seperate test for each supply I have, and add numerical values in the...
    Posted to Custom IC Design (Forum) by Tobben24 on Mon, Mar 18 2013
  • ADE XL Bug?

    Hi, After running a MC run with signals with the same name between test benches I get a bug when trying to open/close(click on + or - icon on left side) summary. What happens is the when I want to close a signal summery(click on the minus icon), the summary collapse as we get a single line with information...
    Posted to Custom IC Design (Forum) by Tobben24 on Mon, Mar 18 2013
  • Reopen MC results after closing adexl

    Hi, I have runned a MC run using adexl, and got a nice overview of results, spec etc. Then I closed adexl, and when I reopened the adexl view the results tab was empty. Is it possible to me get this overview back in the results tab? All the files from the simulation was stored.
    Posted to Custom IC Design (Forum) by Tobben24 on Mon, Mar 18 2013
  • PWL filename

    Hi, I'm wondering in what folder you are when you specify PWL file name for a ipwlf symbol? Cannot find any info on this in documentation.
    Posted to Custom IC Design (Forum) by Tobben24 on Wed, Dec 5 2012
  • Continue simulation after it is finished

    Hi, Is it possible to continue a simulation after it is finished? I mean, if you run a simulation and after it is done you see on the plot that you should have runned it a few us longer.
    Posted to Custom IC Design (Forum) by Tobben24 on Thu, Nov 29 2012
  • ADEXL: Change config file and re-run simulation automatically

    Hi, I want to do the following 5 times with a new schematic view every time: 1. Run a simulation 2. Switching schematic view on one cell in the config file and re-run Any one have a good advice on how to do this in ADEXL? I could create 5 tests with 5 different config files? Or is a Cell View restricted...
    Posted to Custom IC Design (Forum) by Tobben24 on Tue, Nov 27 2012
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