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  • Problem in viewing grid during Layout

    Sir/Madam, I have been using Cadence Virtuoso and the process chosen is 65nm CMOS . While trying to Layout a design it is found that the grid is not visible but if we zoom till only one transistor, the grids become visible. My querry is Is there any issue if grid is not visible while doing Layout...
    Posted to Custom IC Design (Forum) by Jithin on Mon, Aug 19 2013
  • Re: Plotting through calculator

    HI, Thank you for the faster reply once again. What I have been doing in my design is just sweeping the gate voltage of an nmos transistor(65 nm cmos process), while keeping the transistor in saturation. The problem I have faced while doing experiment is that I was not able to plot the output using calculator...
    Posted to Custom IC Design (Forum) by Jithin on Wed, Jun 5 2013
  • Plotting through calculator

    Hi, I have been plotting a Ids vs Vds curve of nmos in 65 nm process and been saving all the parameters using the script "save M0.m1 :all" but the problem I am facing is that when I try to plot the current of transistor throgh the calculator an error is coming saying "Illegal expression...
    Posted to Custom IC Design (Forum) by Jithin on Thu, May 30 2013
  • compatibility of Assura 3.1 for 65 nm process

    Hi, I have been using Assura 3.1 for DRC,LVS and extraction for 0.35 um cmos process and now we have been using 65 nm process. Does this Assura is capable for DRC, LVS and including extraction for 65 nm cmos process.
    Posted to Custom IC Design (Forum) by Jithin on Sat, May 25 2013
  • Generating LEF from layout view

    Hi all! I have been trying to export LEF from standard cells layout in order to use that LEF file in Encounter for automatic PnR. From virtuoso I select File -> Export -> LEF and fill the form appropriately but the lefout.log is giving a warning on metal 4 as shown below: Warning (OALEFDEF-50144...
    Posted to Custom IC Design (Forum) by BraveHeart on Tue, Jun 12 2012
  • montecarlo simulations beetween Wmin and Wmax for mos transistors

    Hi, I'm working with virtuoso 6.1.3. I'd would like to evaluate performances for a circuit when width for each mos transistors are bounded beetween values Wmin and Wmax (such as w=2u to w=20u for instance). Is there a way to run randomly a lot of simulations taking account such constraints (beetween...
    Posted to Custom IC Design (Forum) by inessadm on Sun, May 6 2012
  • Assura41 ELW, VLW resize: CPU load 101%

    ****************************** The problem was happen after checked DRC. ********************************** The Error Layer Window and VLW keep resize. The user's CPU load on share server is 101%. ***************************************************************************************************...
    Posted to Custom IC Design (Forum) by LayMan on Tue, May 1 2012
  • Running Cadence IC on VMware?

    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012
  • Re: How to perform Post-Layout simulations using UltraSim for Black-Box Cells?

    Hi Quek Thanks for your reply. I specified the dpf file as per your advice and the simulation has completed successfully and a graph is also plotted but results are not correct! Actually ultrasim is not able to find the 'INVXL' subcircuit. (which is Artisan's standard cell). Here is the message...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 26 2011
  • Plotting new post-simulation outputs in ADEXL

    Hi, I'm using IC6.1.3.500.11. I have a pretty simple problem which I can't seem to find the solution to. After finishing a simulation in ADE XL and changing or adding some expressions in my 'Outputs Setup' window, the new expressions are not reflected in the 'Results' tab. It...
    Posted to Custom IC Design (Forum) by blorbx on Wed, May 11 2011
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