Home > Community > Tags > 5.1.14/layout
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • pins visible but pin names invisible in instance in layout/layout XL

    We have a problem in 5.1 layout or layout XL that some of the pins we put in our layout (at the top level of a large design) do not show visible names when we instance the cell at the next level up and hide the insides (using ^f), even after turning on the editor display options "instance pins"...
    Posted to Custom IC Design (Forum) by tdtg on Fri, Nov 2 2012
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
Page 1 of 1 (2 items)