will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > 5.1.14
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Encounter Netlist files

    Hello! If I have a transistor level schematic and my simulations show that my circuit is working correctly in virtuoso, how can I generate the verilog netlist and source code to be imported/included for Encounter to design the layout? Thanks in advance!
    Posted to Custom IC Design (Forum) by EveBell on Tue, Mar 29 2011
  • Open Instance connections Assura LVS error

    Simple inverter as a Ring Oscillator Design is DRC clean but the Assura LVS brings up Nets Mismatch Tool...Open Instance Connections... I've tried severval ways to remove error but to no avail. Any insight will be appreciated. attach are the screen shot
    Posted to Custom IC Design (Forum) by jdgriggs on Mon, Oct 11 2010
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
  • About the spectre pss problem

    Hi, deal all: I use the old version of spectre (ver 5.10.41), when I do a vco pss analysis , I found the spectre can't catch the frequency of the vco. For example , before the pss analysis a run a tran analysis. measure the freq=1.4617G(when the vco have reach the stable state);but in the following...
    Posted to Custom IC Design (Forum) by kivvzhou on Mon, Mar 15 2010
  • problem with mmsim61

    i've just finished the installation of cadence ic5141 and mmsim61 and configuration. when i simulating a simple inverter circuit in ADE,it gives the error messages below: cpp: unrecognized option `-$' Environment variable: SPECTRE_DEFAULTS=-E Command line: /usr/eda/cadence/MMSIM61/tools.lnx86...
    Posted to Custom IC Design (Forum) by minci on Thu, Feb 11 2010
  • problem in spectre

    hi,there i'm using ic5141 usr6 to design. In our new project,we'll use the IBM PDK cmrf8sf.but i found the spectre in ic5141 is not supporting the new bsim4 model.Then,i use +csfe option in the usrCmdLineOption of spectre environment options,and this will work. When i've re-installed my OS...
    Posted to Custom IC Design (Forum) by minci on Mon, Feb 1 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
  • Import spectre netlist

    Hello all, I have to look for real differences of subcircuits in two spectre netlists. It should be the same circuit, but the names of the nets and instances seemes to be compleetly different. My idea is to cut out the parts of the subcircuits definition, import them to a cell (IC5.141) and use the LVS...
    Posted to Custom IC Design (Forum) by Bernd das Brot on Fri, Jan 8 2010
  • Parameter Arrays in Cadence Schematic

    Hi, I am using icfb ic-5.1.14, and I have a question about adding parameters in a symbol array in schematic. For example, I have an instance array I<1:2> , and each instance has a parameter called length. I want to give the first instance a length parameter of "5", the second one "6"...
    Posted to Custom IC Design (Forum) by gokce on Fri, Sep 25 2009
Page 2 of 2 (19 items) < Previous 1 2