Home > Community > Tags > 5.1.14
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • Re: Error (VACOM-1008) - Cannot compile ahdlcmi module library (MMSIM.07.11)

    Hi Saber, RE: ldd /CMC/tools/cadence/IC.5141.USR5.linux/tools.lnx86/spectre/bin/32bit/spectre 1. You do not want to use ic5141 spectre... ever . That technology hasn't been supported in over 10 years! You have to use spectre from the MMSIM hierarchy. And you should be using MMSIM 12.1.1 spectre....
    Posted to Custom IC Design (Forum) by Tawna on Thu, Aug 15 2013
  • "Error(s) found during netlisting. The netlist may be corrupt"

    Hi, I'm using IC5.1.41 and everytime I start a new simulation, I get this error message. Even when the circuit has not been changed. One example is that, suppose I start an ADE session with design 1, which has been checked and saved (with no errors/warnings); run a simulation and then close the design...
    Posted to Custom IC Design (Forum) by NcfC on Thu, May 30 2013
  • pins visible but pin names invisible in instance in layout/layout XL

    We have a problem in 5.1 layout or layout XL that some of the pins we put in our layout (at the top level of a large design) do not show visible names when we instance the cell at the next level up and hide the insides (using ^f), even after turning on the editor display options "instance pins"...
    Posted to Custom IC Design (Forum) by tdtg on Fri, Nov 2 2012
  • Checking error status after SKILL function execution.

    E.g. after running command amsProcessCellViews("test", "decoder", "verilogams" ?checkOnly t ?netlist t ?compile t ?netlistMode `all ?compileMode `all) I receive message "Error: ncvlog failure on the Verilog-AMS file..." in CIW and returned function value 't'...
    Posted to Custom IC Design (Forum) by Runner on Sun, May 27 2012
  • ADE Licence Management

    I am looking for a way to manage our ADE licence such that it is released once user A is done with his task and user B can grab the licence without waiting for user A to manually checkin the licence. Is there an environment variable that I can set using the envSetVal("asimenv[.partition]" "variable"...
    Posted to Custom IC Design (Forum) by Xegotronix on Mon, Sep 12 2011
  • Why OCEAN script produce different analysis result from ADE?

    Hi, I uses a scripts to analyze phase noise of a VCO at different control voltage. I found some data points are significantly different from ADE produced. Then I saved script in ADE and load the script in ocean. The phase noise calculated with ocean script is -80. But at ADE, it is -100. Anyone can tell...
    Posted to Custom IC Design (Forum) by datao on Thu, Jul 7 2011
  • Exporting files

    Hello, Is it possible to export my spectre netlist file generated from my schematic into another environment so that I could use it as an input file for matlab and visual c++? Thx!
    Posted to Custom IC Design (Forum) by EveBell on Wed, Apr 27 2011
  • AC vs. PZ analysis

    I have a complex opamp model built using ideal sources (no transistors models). I am interested in frequency response, so tried both AC and PZ analysis, to check the dominant pole (-3 dB), resulting as: AC @ 59.24 MHz , and PZ @ 60.18 MHz. This is fairly close, then i compensate the model (miller compensation...
    Posted to Custom IC Design (Forum) by ASICnm on Wed, Apr 20 2011
  • IC5141 problem on rhel5

    I have installed ic5141(sub-version on rhel5.3/5.4 It's view flowing msg when close CIW windows it's only show when open any schmatic hosts> libgcc_s.so.1 must be installed for pthread_cancel to work
    Posted to Custom IC Design (Forum) by edafans on Wed, Apr 13 2011
  • setup Distibuted processing in ADE L

    I'm installed ic5141( subversion 135) on rhel5 and configured SGE 6U4 Have queue on SGE cluster: all.q (8 hosts) 2host.q (2 hosts) I have read the distproc.pdf file I'm vi a queue_config_file for flowing all.q 8 2host.q 2 I hat to set :setenv LBS_CLUSTER_MASTER mnode ; setenv LBS_BASE_SYSTEM...
    Posted to Custom IC Design (Forum) by edafans on Mon, Apr 11 2011
Page 1 of 2 (19 items) 1 2 Next >