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Send Yourself A Copy
3d-ic,SiP
2.5D
2.5D IC
3D
3D IC
3D IC ecosystem
3DIC
Allegro
Allegro 16.3
Analog and RF SiP design
analysis
APD
Cadence
Chip Scale Review
codesign
Co-Design
CoWoS
DAC
Digital SiP desgn
Digital SiP design
Encounter
extraction
foundry
GSA
GSA 3D IC
IC Package Physical layout and co-design
IC packaging
IC Packaging & SiP design
IC Packaging and SiP
iJTAG
Industry Insights
interposer
Ken Potts
Kevin Rinebold
Kulicke & Soffa
OSAT
OSATs
package
PI
Potts
power density
power integrity
QRC
routing
SI
Si2
signal integrity
silicon interposer
Silicon Realization
SoC
SPB
SPB16.3
stacked die
Standards
system co-analysis
system planning
Team Allegro
test
thermal
thernal
TSMC
TSV
TSVs
tutorial
via
Virtuoso
wide i/o
wide io
wirebond profile library
Leverage System Planning to Maximize Performance of Silicon Interposer
Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Thu, Dec 6 2012
TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem
Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate ( CoWoS ) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 4 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 21 2012
New Silicon Realization Design Methodology Boosts 3D ICs With TSVs
Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 31 2011
Favorite Features Of An IC Package Designer: Assembly Rule Checks
This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the question of "Can this be manufactured?"...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Wed, Jul 28 2010
Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats
This is the second in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. Recently on a visit to an avid user of IC Package design tools, we heard the requirement mantra of efficiency and flexibility. Many package designers...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Thu, May 20 2010
Favorite Features of an IC Package Designer: Flexible 3D Viewing
This is the first in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. We talk to customers all the time that are designing IC packages with stacked die. While trough-silicon-via (TSV) is the wave of the future, the vast majority...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Wed, Apr 28 2010
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