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3D-IC
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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment
3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 23 2013
TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 14 2013
CDNLive Silicon Valley 2013 Proceedings Available for Download!
CDNLive Silicon Valley, held March 12-13, 2013, featured nearly 100 technical sessions from customers, partners, and Cadence R&D experts. Presentations from most of those sessions are now available on line . Here's your chance to review presentations you heard, catch up on sessions you missed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Apr 4 2013
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics, and How Cadence Can Help
Lip-Bu Tan, Cadence president and CEO, is excited about ongoing innovation within the electronics industry - but he's also aware of challenges such as advanced node lithography, complexity, time-to-market, and rising design costs. In a keynote speech at the CDNLive Silicon Valley conference March...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 12 2013
Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013
If you're familiar with the popular, cutting-edge TED Talks lecture series, then I would call the Electronic Design Process Symposium ( EDPS ) the "TED Talks" of EDA. Now in its 20 th year, this IEEE-sponsored workshop brings together the thinkers, movers and shakers of IC and systems design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 11 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond
How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 6 2013
Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic
3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 22 2013
Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs
In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design products in the Silicon...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 12 2012
Leverage System Planning to Maximize Performance of Silicon Interposer
Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products...
Posted to
IC Packaging and SiP
(Weblog)
by
TeamAllegro
on Thu, Dec 6 2012
Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs
T he recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here . Separately, I interviewed one...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 24 2012
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