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3D-IC

14nm
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3D IC
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12 Hot EDA Topics – 78 DAC Demo Sessions

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 24 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 21 2012
See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 25 2012
Panelists: What Needs to Happen for 3D-IC TSV Success

It's time to get to work if we want to bring 3D-ICs with through-silicon vias (TSVs) into the semiconductor design mainstream. What ecosystem support is needed in the short term, medium term, and long term to make this new technology successful? That's the question that was put to a panel of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 11 2012
EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 10 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs

What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 9 2012
TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

The world's largest foundry provider, TSMC, is confident it can keep up with the semiconductor scaling predicted by Moore's Law and can even outpace Moore's Law through 2.5D and 3D-ICs. It's all part of the "incredible high-tech future" predicted by Rick Cassidy, president of...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 14 2012
Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More

If you want a deeper understanding of the challenges, trends, and potential new solutions for IC and systems design, there's no better place to find out than the IEEE-sponsored Electronic Design Processes Symposium (EDP) April 5-6, 2012, in Monterey, California. Now in its 19 th year, this interactive...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 8 2012
Top Ten Cadence Community Blog Posts of 2011

Over 430 Cadence Community blog posts appeared in 2011, in categories including Industry Insights, Functional Verification, PCB Design, System Design & Verification, Custom IC, Digital Implementation, RF, Mixed Signal, and Low Power. By looking at the most widely-read posts, we can get a picture...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 1 2012
2011 EDA Standards Update and 2012 Forecast

As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 21 2011

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3D-IC

12 Hot EDA Topics – 78 DAC Demo Sessions

Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

Panelists: What Needs to Happen for 3D-IC TSV Success

EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

EDA Symposium: Users Cite 3D-IC Design Tool Needs

TSMC CDNLive! Keynote – “We Can Beat Moore’s Law”

Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More

Top Ten Cadence Community Blog Posts of 2011

2011 EDA Standards Update and 2012 Forecast