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3D IC

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013

If you're familiar with the popular, cutting-edge TED Talks lecture series, then I would call the Electronic Design Process Symposium ( EDPS ) the "TED Talks" of EDA. Now in its 20 th year, this IEEE-sponsored workshop brings together the thinkers, movers and shakers of IC and systems design...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 11 2013
Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

3D-ICs that combine memory and logic promise tremendous benefits for low-power mobile applications, but design for test (DFT) remains a major concern. This week (Jan. 22, 2013) Cadence and the Belgian research institute imec are reporting progress with an automated DFT solution for memory-on-logic 3D...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 22 2013
Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs

In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design products in the Silicon...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 12 2012
Leverage System Planning to Maximize Performance of Silicon Interposer

Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet the challenges of developing electronic products...

Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Thu, Dec 6 2012
A New Information Resource for 3D-IC TSV Design

A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor IP solutions, it includes press releases, blog posts, whitepapers, articles, and an archived webinar...

Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 16 2012
Si2 DAC Panel: What Standards are Needed for 3D-ICs?

3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 28 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate ( CoWoS ) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 4 2012
12 Hot EDA Topics – 78 DAC Demo Sessions

Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 24 2012

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3D IC

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Join EDA “Movers and Shakers” at Electronic Design Process Symposium (EDPS) April 18-19, 2013

Cadence, Imec Develop Test Methodology for 3D-IC Memory on Logic

Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs

Leverage System Planning to Maximize Performance of Silicon Interposer

A New Information Resource for 3D-IC TSV Design

Si2 DAC Panel: What Standards are Needed for 3D-ICs?

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

12 Hot EDA Topics – 78 DAC Demo Sessions