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28nm

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 14 2013
Archived Webinar: Variation-Aware Analysis for Advanced Node Design

Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...

Posted to Industry Insights (Weblog) by rgoering on Sun, Nov 11 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...

Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 5 2012
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 17 2012
Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling

A re we heading for a major retooling in custom IC design? EDA veteran Jim Hogan thinks so, and in a keynote speech at the Silicon Integration Initiative ( Si2 ) Conference Oct. 9, 2012, he argued that the consumer electronics marketplace will drive a new era he calls "Custom 2.0." The Si2...

Posted to Industry Insights (Weblog) by rgoering on Thu, Oct 11 2012
Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...

Posted to Low Power (Weblog) by Pete Hardee on Mon, Sep 17 2012
ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow

For several years, ARM has offered processor optimization utilities (called POPs) that help users of ARM Cortex-A series processors optimize power, performance and area for a given process. This week (Aug. 9) ARM and Cadence took things one step further by announcing a POP that includes scripts that...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 9 2012
20 Questions on 20nm – And a New Resource for Advanced Node Design

If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jul 26 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 12 2012
What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is...

Posted to Mixed-Signal Design (Weblog) by QiWang on Thu, May 31 2012

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28nm

TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies

Archived Webinar: Variation-Aware Analysis for Advanced Node Design

Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

Si2: Jim Hogan Predicts “Custom 2.0” IC Design Retooling

Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow

20 Questions on 20nm – And a New Resource for Advanced Node Design

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

What’s Hot for Mixed-Signal At DAC?