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Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums
The recently concluded ARM TechCon 2012 , the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Wed, Nov 14 2012
Whitepaper: New Methodology Needed for 20nm Custom/Analog IC Design
Before digital SoC designers take advantage of the power, performance and density advantages of 20nm, custom/analog designers must develop the standard cells and the analog/mixed-signal IP. Thus, no 20nm solution is complete without an integrated custom/analog capability. A newly published Cadence whitepaper...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 13 2012
Archived Webinar: Variation-Aware Analysis for Advanced Node Design
Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Nov 11 2012
Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges
Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 5 2012
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Nov 2 2012
Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs
T he recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here . Separately, I interviewed one...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 24 2012
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 17 2012
Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions
Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept. 20, 2012. While panelists noted progress in mixed-signal design tools and flows, they pointed to a number...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 1 2012
20 Questions on 20nm – And a New Resource for Advanced Node Design
If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jul 26 2012
User View: A 20nm Custom IC Constraint-Driven Flow
If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jul 25 2012
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