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Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support
I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look...
Posted to
Custom IC Design
(Weblog)
by
stacyw
on Mon, May 13 2013
EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to parasitic extraction. FinFET extraction challenges...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 29 2013
TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Apr 14 2013
Cadence Cosmic Circuits Acquisition – Analog/Mixed Signal IP for Advanced Node SoCs
Last week (Feb. 7, 2013) Cadence announced an agreement to acquire Cosmic Circuits Private Limited, a leading provider of analog/mixed-signal IP based in Bangalore, India. Here's some background on this relatively young, fast-growing company, and how its offerings fit into the growing Cadence design...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 11 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond
How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 6 2013
Introduction to Cadence Virtuoso Advanced Node Design Environment
What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...
Posted to
Custom IC Design
(Weblog)
by
Hiro Ishikawa
on Mon, Jan 28 2013
Virtuoso Advanced Node: Analyzing Layouts Before They’re Done
One paradox of advanced node (28nm and below) custom IC design is that the layout "context" -what is placed near to a device - can change the performance of a device by as much as 30%. Thus, designers must be able to predict layout-dependent effects (LDE) before the final layout is completed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 28 2013
Top Ten Cadence Community Blog Posts of 2012
In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 1 2013
Video, Presentation – Low Power Design with ARM Physical and Processor IP
Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 17 2012
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip
All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 27 2012
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