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20 nm,Industry Insights,test chips,Double Patterning,EE Times,Cortex-A15,DFM,variation,extraction
20nm webinar
ARM
Cadence
ccopt
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clock concurrent optimization
Desharnais
EDA
Encounter
FlexModels
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giga-scale
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mask misalignment
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variability
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 2 2012
Page 1 of 1 (1 items)