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16nm,Virtuoso

  • Top Ten Cadence Community Blog Posts of 2013

    In 2013, Cadence Community bloggers published over 375 posts in categories including Industry Insights, Functional Verification, Fuller View, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing, in order...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Dec 15 2013
  • TSMC 3D-IC Reference Flow Supports 3D Die Stacking

    An important milestone for any new semiconductor technology is the availability of a foundry EDA reference flow. Such a milestone occurred last week (Sept. 18, 2013) as Cadence and TSMC delivered the latest Cadence 3D-IC reference flow for true 3D die stacking (right). While there has been considerable...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 24 2013
  • TSMC Native SKILL PDKs Tune Virtuoso for 16nm FinFET Design

    Custom/analog designers working at FinFET process nodes are going to need all the help they can get. As announced by Cadence today (July 8, 2013), TSMC will help out by providing native SKILL-based process design kits (PDKs) for the TSMC 16nm FinFET process. TSMC is also expanding its usage of the Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jul 8 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Top Ten Cadence Community Blog Posts of 2012

    In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation. Below is a listing of the ten most read...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 1 2013
  • TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

    TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 17 2012
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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