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  • DRC Error: Package to Room Spacing

    Hi everybody, I am designing my PCB (OrCAD 16.6). When I place parts of a room I see below message: Class: DRC ERROR CLASS Subclass: PACKAGE_BOTTOM Origin xy: (1068.00 178.00) Constraint: Package to Room Spacing Constraint Set: NONE Constraint Type: DESIGN Constraint value: 0 MIL Actual value: 65 MIL...
    Posted to PCB Design (Forum) by Hossein1357 on Sat, Jul 26 2014
  • Place Replicate Unmatch!..

    Hi, I am designing my PCB with 16.6. I placed components of a Room and made a replicate module. When I try to apply replicate to other similar Rooms, "Unmathced Component Interface" dialoge appears and lists nearly all of modules parts as unmatched. I am pretty sure that these groups of symbols...
    Posted to PCB Design (Forum) by Hossein1357 on Mon, Jul 21 2014
  • Dynamic Shape out of date, but not accessible.

    Hi All, I'm almost finished with my very first board layout using Allegro PCB editor 16.6 (latest hotfix June 2014), and I'm trying to generate the artwork so I can check over it and make sure it's good to send out to manufacturing. I'm having a problem when I try to create the artwork...
    Posted to PCB Design (Forum) by mwaskett on Tue, Jul 8 2014
  • What's Good About Allegro PCB Editor Design Partitioning? 16.6 Has Several New Enhancements!

    The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the PCB Design team experiences in the physical team design flow. Flexible Boundaries Designed to reduce...
    Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Jun 23 2014
  • Bad PSpice net name on part

    Hi, I am trying to simulate the fulladd circuit which is there in <install dir>\Cadence\SPB16.6\doc\flowtut\complete\fulladd.dsn. I am getting this error Bad PSpice net name on part. Thanks
    Posted to PCB Design (Forum) by vin5488 on Thu, Jun 19 2014
  • Orcad Capture Netlist Error!

    Hi everyone, So I'm new to Orcad and trying to create a netlist to do layout using Allegro PCB Editor. I get the ORCAP-32042 error when trying to make a netlist so I look at the netlist log file and see the following error: " Error at line 252 in file C:\USERS\RSTARK\DESKTOP\ATLAS/pstxnet.dat...
    Posted to PCB Design (Forum) by StStark on Tue, Jun 10 2014
  • What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6 Has It!

    The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below. Read on for more details … IPC 2581 Overview PCBs have changed significantly over the past three decades, yet...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jun 10 2014
  • Keep power nets separate in a hiearchical design

    Hello, Say that I instantiate the same block four times in a schematic, I’m using the SUBDESING_SUFFIX attribute to keep the same location value in each instance, for example, R1 becomes R1CH1 in channel 1, R1CH2 in channel 2 and so forth. Even though all four blocks are identical I want to use...
    Posted to PCB Design (Forum) by Mattias J on Wed, Jun 4 2014
  • What's Good About Allegro PCB Editor Offset Routing? 16.6 Has a Few New Enhancements!

    The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while routing across fiberglass substrates. Other routing applications may be applicable as a result of this implementation...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, May 27 2014
  • CIS connected to MySQL database

    I tried to configure CIS to my Enterprise MySQL Database but Orcad return the follow error message: ERROR(ORCIS-6233): The Table Property Type of the field PartNumber in table Resistors is not of type TEXT, STRING or CHARACTER. The Table Property Type of the field assigned as Property Type Part_Number...
    Posted to PCB Design (Forum) by stetag on Tue, May 6 2014
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