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Send Yourself A Copy
16.5
"capture CIS"
"PCB design"
"PCB PI"
"PCB SI"
.brd Viewer
.psm
16.01
16.2
16.3
16.6
3D viewer
Allegro
Allegro 16.3
Allegro 16.5
Allegro 16.6
Allegro Design Entry
Allegro PCb
Allegro PCB Design XL
Allegro PCB Editor
allegro PCB Editor drill error
Allegro PCB SI
Allegro performance
Allegro System Administration
Allegro System Architect (ASA)
allegro viewer macro
AllegroPI
AMS simulation
AMS simulator
application mode
application note
applications
Appnote
Appnotes
array
assembly drawing
auto router
automatic router
autorouter
back annotate
batch edit
Cadence
Cadence 16.5
Cadence Allegro
Capture
Capture 16.5
Capture CIS
Capture-CIS
ConceptHDL
Constraints
customer support
DEHDL
design
Design Entry
Design Entry CIS
Design Entry HDL
Differential Pair Support
Differential pairs
double layer
drc
DRC error
DRC rules
DXF Import
dxf2a
etch class
feedback regulation loops
flat schematics
Footprint
Footprint catalog PCB Editor
footprint creation
Footprint in 3D
force sense
hierarchical schematics
hierarchy
High Speed
Kelvin
layout
libraries
Library
netlist
Orcad
OrCAD 16.5
OrCAD Capture
OrCAD Capture 16.5
OrCAD PCB Editor
PCB
PCB Capture
PCB design
PCB Designer
pcb editor
PCB layout
PCB Layout and routing
PCB SI
Schematic
shape
Shape Fill
SPB
SPB16.3
SPB16.5
via
vias
Forcing via connections
I have a multi-layer design with multiple ground plane layers. But these have issues with ground loops. How can I set something in PCB Editor 16.5 that will only connect vias to one ground plane layer and leave all other layers unconnected, so that I can use a single ground connection point.
Posted to
PCB Design
(Forum)
by
tmd63
on Fri, May 3 2013
Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture
Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized. Annotation is the automated process...
Posted to
PCB Design
(Weblog)
by
Naveen
on Thu, May 2 2013
How to import and export constraints from Allegro PCB to Excel
We have some complex and large constraints files to use for our designs and it would make life a lot easier if the constraints could be downloaded to excel, modified and then reloaded back into the design. Is there any way that this can be done.
Posted to
PCB Design
(Forum)
by
tmd63
on Wed, May 1 2013
DRC T error
I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
Posted to
PCB Design
(Forum)
by
tmd63
on Fri, Apr 19 2013
Generating a BOM
Has anyone generated a BOM from OrCAD like this? I use version 16.5 here. I get close with variant report but I am not there yet. Any suggestions would be very welcome. Quantity#Part Reference#PART_NUMBER#VARIANT#LAYER 1#PCB1#P00001-1#1,2,#t 1#C1#P00002-0212#1,2,#t 1#C2#P00006-102#1,2,#b 1#C3#P00007...
Posted to
PCB Design
(Forum)
by
Garry
on Tue, Apr 16 2013
DXF import into Allegro 16.3 / 16.5
I have used dxf imports before in Layout 15.7 and we had a simple way to use layers for the basic designs and then import a v12 dxf. But when I try to develop a basic board outline for Allegro 16.3 or 16.5, there does not appear to be a way of importing the plated and non-plated holes into a PCB. What...
Posted to
PCB Design
(Forum)
by
tmd63
on Wed, Apr 10 2013
Via capacitance
Hi, I am currently using Allegro 16.5. Pls let me know if there is any option to find out Via Capacitance . Thanks Bala R
Posted to
PCB Design
(Forum)
by
Bala R
on Wed, Apr 3 2013
allegro sp 16.5 lite - "error(spmhod-29)"
Hi, i'm new to pcb design tool , i received some .brd and .dra and .psm file from my friend for my practice, he did this on Allegro sp 16.6 but i'm using Allegro sp 16.5 lite version. when i open those file i receive the following error. ERROR(SPMHOD-29): Unable to open design because database...
Posted to
PCB Design
(Forum)
by
ping2murali
on Wed, Mar 27 2013
Customer Support Recommended – Regulation Loop Design Using Allegro AMS Simulator (PSpice)
Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage droops. In order to achieve a stable and...
Posted to
PCB Design
(Weblog)
by
Naveen
on Wed, Mar 20 2013
Static shapes not displaying solid.
I have a couple of shapes used for edge protections etc which are static shapes to ensure that tracks do not destroy the protection provided. But when I try to see them onscreen, the filled area is a mesh of dots instead of a solid area. If I switch it to a dynamic shape, the display shows a solid area...
Posted to
PCB Design
(Forum)
by
tmd63
on Fri, Mar 1 2013
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