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16.5,DRC error

  • DRC T error

    I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
    Posted to PCB Design (Forum) by tmd63 on Fri, Apr 19 2013
  • Line to Shape Spacing DRC on Every Trace

    Hello, I am just starting out with OrCAD 16.5 and I had a few questions. 1. I have imported a design from Capture but in connecting the traces I have a "Line to Shape Spacing" DRC at pretty much every 45* angle junction. It says "constraint value 5mil, actual value 0mil." It's...
    Posted to PCB Design (Forum) by Grue42 on Tue, Oct 23 2012
  • Edit-Copy generates DRC "Line to thru pin spacing" errors

    Am I missing something on how to make an array of boards? I chose Edit - Copy, provided the spacing I wanted for the boards, the number of boards to create, then clicked "All On" for the "Find" filter. I drew a box around the board, picked my origin, and then placed the new array...
    Posted to PCB Design (Forum) by admin on Thu, Aug 30 2012
  • Allegro PCB Designer : Interlayer Spacing ?

    Hi, I'm currently working with Cadence 16.5 and I would like to add an interlayer spacing constraint for two adjacent layers, in order to prevent interlayer crosstalk between differential pairs. I spent some hours looking for a solution, and I found this post : http://www.cadence.com/Community/forums...
    Posted to PCB Design (Forum) by mxlecanu on Thu, Jul 26 2012
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